LAN9211 datasheet(32/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

Note: When the TXCOE is enabled, the third DWORD of the pre-pended packet is not transmitted.

However, 4 bytes must be added to the packet length field in TX Command ‘B’.

Note: The TX checksum preamble must be DWORD-aligned (i.e., the two least significant bits of the

Data Start Offset fields in TX Command “A” must be zero). Any valid buffer end alignment

setting can be used.

Note: Software applications must stop the transmitter and flush the TX data path before changing the

state of the TXCOE_EN bit. However, the CK bit of TX Command ‘B’ can be set or cleared on

a per-packet basis.

3.6.2.1

TX Checksum Calculation

The TX checksum calculation is performed using the same operation as the RX checksum shown in

Section 3.6.1.1, with the exception that the calculation starts as indicated by the preamble, and the

transmitted checksum is the one’s-compliment of the final calculation.

Note: When the TX checksum offload feature is invoked, if the calculated checksum is 0000h, it is

left unaltered. UDP checksums are optional under IPv4, and a zero checksum calculated by

the TX checksum offload feature will erroneously indicate to the receiver that no checksum was

calculated, however, the packet will typically not be rejected by the receiver. Under IPv6,

however, according to RFC 2460, the UDP checksum is not optional. A calculated checksum

that yields a result of zero must be changed to FFFFh for insertion into the UDP header. IPv6

receivers discard UDP packets containing a zero checksum. Thus, this feature must not be

used for UDP checksum calculation under IPv6.

3.7

Host Bus Operations

3.7.1

Bus Writes

The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD

transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot

change during a sixteen bit write). No ordering requirements exist. The processor can access either

the low or high word first, as long as the next write is performed to the other word. If a write to the

same word is performed, the LAN9211 disregards the transfer.

Table 3.7 TX Checksum Preamble

FIELD

DESCRIPTION

31:28

RESERVED

27:16

TXCSLOC - TX Checksum Location

This field specifies the byte offset where the TX checksum will be inserted in the TX packet. The

checksum will replace two bytes of data starting at this offset.

Note:

The TX checksum cannot be inserted in the MAC header (first 14 bytes) or in the last 4

bytes of the TX packet.

15:12

RESERVED

11:0

TXCSSP - TX Checksum Start Pointer

This field indicates start offset, in bytes, where the checksum calculation will begin in the associated

TX packet.

Note:

The data checksum calculation must not begin in the MAC header (first 14 bytes) or in

the last 4 bytes of the TX packet.

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