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LAN9211 数据表(PDF) 36 Page - SMSC Corporation

部件名 LAN9211
功能描述  High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
PDF  147 Pages
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制造商  SMSC [SMSC Corporation]
网页  http://www.smsc.com
标志 SMSC - SMSC Corporation

LAN9211 数据表(HTML) 36 Page - SMSC Corporation

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
Revision 2.9 (03-01-12)
36
SMSC LAN9211
DATASHEET
3.8
General Purpose Timer (GP Timer)
The General Purpose Timer is a programmable block that can be used to generate periodic host
interrupts. The resolution of this timer is 100uS.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting
down when the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from
set ‘1’ to cleared ‘0,’ the GPT_LOAD field is initialized to FFFFh. The GPT_CNT register is also
initialized to FFFFh on a reset. Software can write the pre-load value into the GPT_LOAD field at any
time; e.g., before or after the TIMER_EN bit is asserted. The GPT Enable bit TIMER_EN is located in
the GPT_CFG register.
Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is
written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT
interrupt status bit and the IRQ signal if the GPT_INT_EN bit is set, and continues counting. The GPT
interrupt status bit is in the INT_STS Register. The GPT_INT hardware interrupt can only be set if the
GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only
be cleared by writing a ‘1’ to the bit.
Table 3.8 Endian Ordering Logic Operation
FIFO Access via Data
FIFO Port (00h-3Ch)
Direct FIFO Access via
FIFO_SEL
CSR Access
Host Data Bus
Host Data Bus
Host Data Bus
D[15:8]
D[7:0]
D[15:8]
D[7:0]
D[15:8]
D[7:0]
FPORTEND=0
FSELEND=0
A1=1
3
2
323
2
A1=0
1
0
101
0
FPORTEND=1
FSELEND=0
A1=1
0
1
323
2
A1=0
2
3
101
0
FPORTEND=0
FSELEND=1
A1=1
32
0
13
2
A1=0
10
2
31
0
FPORTEND=1
FSELEND=1
A1=1
0
1
0
13
2
A1=0
2
3
2
31
0
FPORTEND=0
FSELEND=0
A1=1
1
0
101
0
A1=0
3
2
323
2
FPORTEND=1
FSELEND=0
A1=1
2
3
101
0
A1=0
0
1
323
2
PORTEND=0
FSELEND=1
A1=1
10
2
31
0
A1=0
32
0
13
2
PORTEND=1
FSELEND=1
A1=1
2
3
2
31
0
A1=0
0
1
0
13
2



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