| 数据搜索系统,热门电子元器件搜索 |
|
LAN9211 数据表(PDF) 130 Page - SMSC Corporation |
|
|
|||||||||||||||||||||||||||||
LAN9211 数据表(HTML) 130 Page - SMSC Corporation |
|
130 / 147 page ![]() High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support Datasheet Revision 2.9 (03-01-12) 130 SMSC LAN9211 DATASHEET 6.3 PIO Burst Reads In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between bursts for the period specified. Note: The “Data Bus” width is 16 bits Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. Figure 6.2 PIO Burst Read Cycle Timing Table 6.4 PIO Burst Read Timing SYMBOL DESCRIPTION MIN TYP MAX UNITS tcsh nCS, nRD Deassertion Time 13 ns tcsdv nCS, nRD Valid to Data Valid 30 ns tacyc Address Cycle Time 45 tasu Address Setup to nCS, nRD valid 0 ns tadv Address Stable to Data Valid 40 tah Address Hold Time 0 ns tdon Data Buffer Turn On Time 0 ns tdoff Data Buffer Turn Off Time 7 ns tdoh Data Output Hold Time 0 ns Data Bus nCS, nRD A[7:5] A[4:1] |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |