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ADRF6820ACPZ-R7 数据表(PDF) 36 Page - Analog Devices |
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ADRF6820ACPZ-R7 数据表(HTML) 36 Page - Analog Devices |
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36 / 45 page ![]() ADRF6820 Data Sheet Rev. C | Page 36 of 45 Address: 0x22, Reset: 0x2A03, Name: VCO_CTL Table 26. Bit Descriptions for VCO_CTL Bits Bit Name Settings Description Reset Access [7:6] LO_DRV_LVL External LO amplitude 0x0 RW 00 −5 dBm 01 −1 dBm 10 +2 dBm 11 +4 dBm 5 DRVDIV2_EN Divide by 2 for external LO driver enable 0x0 RW 0 Disable 1 Enable 4 DIV8_EN Divide by 2 in LO path for total of division of 8 0x0 RW 0 Disable 1 Enable 3 DIV4_EN Divide by 2 in LO path for total of division of 4 0x0 RW 0 Disable 1 Enable [2:0] VCO_SEL Select VCO core/external LO 0x3 RW 000 4.6 GHz to 5.7 GHz 001 4.02 GHz to 4.6 GHz 010 3.5 GHz to 4.02 GHz 011 2.85 GHz to 3.5 GHz 100 External LO/VCO |
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