ADRF6820ACPZ-R7 datasheet(15/45 Pages) AD

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Data Sheet

ADRF6820

Rev. C | Page 15 of 45

RF ATTENUATOR

The RF digital step attenuator (RFDSA) follows the tunable

balun, and the attenuation range is 0 dB to 15 dB with a step

size of 1 dB. The RFDSA_SEL bits (Register 0x23, Bits[8:5]) in

the DGA_CTL register determine the setting of the RFDSA.

LO GENERATION BLOCK

The ADRF6820 supports the use of both internal and external

LO signals for the mixers. The internal LO is generated by an

on-chip VCO, which is tunable over an octave frequency range

of 2850 MHz to 5700 MHz. The output of the VCO is phase

locked to an external reference clock through a fractional-N

PLL that is programmable through the SPI control registers.

To produce in-phase and quadrature phase LO signals over the

356.25 MHz to 2850 MHz frequency range to drive the mixers,

steer the VCO outputs through a combination of frequency

dividers, as shown in Figure 32.

Alternatively, an external signal can be used with the dividers or

a polyphase phase splitter to generate the LO signals in quadrature

to the mixers. In demanding applications that require the lowest

possible phase noise performance, it may be necessary to source

the LO signal externally. The different methods in quadrature

LO generation and the control register programming needed

are listed in Table 9.

Internal LO Mode

For internal LO mode, the ADRF6820 uses the on-chip PLL and

VCO to synthesize the frequency of the LO signal. The PLL,

shown in Figure 32, consists of a reference path, phase and

frequency detector (PFD), charge pump, and a programmable

integer divider with prescaler. The reference path takes in a

reference clock and divides it down by a factor of 2, 4, or 8 or

multiplies it by a factor of 1 or a factor of 2, and then passes it to

the PFD. The PFD compares this signal to the divided down

signal from the VCO. Depending on the PFD polarity selected,

the PFD sends an up/down signal to the charge pump if the

VCO signal is slow/fast compared to the reference frequency.

The charge pump sends a current pulse to the off-chip loop

filter to increase or decrease the tuning voltage (VTUNE).

The ADRF6820 integrates four VCO cores covering an octave

range of 2.85 GHz to 5.7 GHz.

Table 9 lists the frequency range covered by each VCO. The

desired VCO can be selected by addressing the VCO_SEL bits

(Register 0x22, Bits[2:0]).

PFD

CHARGE

PUMP

QUAD

DIVIDER

÷2

N = INT +

FRAC

MOD

POLYPHASE

FILTER

÷1, ÷2,

÷4

LOIN–

VTUNE

EXTERNAL

LOOP

FILTER

LPF

LOIN+

VCO_SEL

REG 0x22[2:0]

DIV8 _EN/

DIV4_EN

REG 0x22[4:3]

DIV_MODE: REG 0x02[11]

INT_DIV: REG 0x02[10:0]

FRAC_DIV: REG 0x03[15:0]

MOD_DIV: REG 0x04[15:0]

CP_CTRL

REG 0x20[13:0]

×1

×2

÷8

÷4

÷2

REFIN

REFSEL

REG 0x21[2:0]

PFD_POLARITY

REG 0x21[3]

TO MIXER

I+

I–

Q+

Q–

QUAD_DIV_EN

REG 0x01[9]

Figure 32. LO Generation Block Diagram

Table 9. LO Mode Selection

LO Selection

fVCO or fEXT (GHz)

Quadrature Generation

QUAD_DIV_EN,

LO Enables,

VCO_SEL,

Internal (VCO)

2.85 to 3.5

Divide by 2

111 111X

011

3.5 to 4.02

Divide by 2

111 111X

010

4.02 to 4.6

Divide by 2

111 111X

001

4.6 to 5.7

Divide by 2

111 111X

000

External (2× LO)

0.7 to 6.0

Divide by 2

101 000X

1XX

External (1× LO)

0.35 to 3.5

Polyphase

000 000X

XXX

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