ADRF6820ACPZ-R7 datasheet(19/45 Pages) AD

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Data Sheet

ADRF6820

Rev. C | Page 19 of 45

Pin No.

Mnemonic

Description

Basic Connection

PLL/VCO

Synthesizer charge pump output voltage

Connect to the VTUNE pin through the loop filter.

REFIN

Synthesizer reference frequency input

Nominal input level is 1 V p-p. Input range is 12 MHz to

320 MHz. This pin is internally biased to VPOS_3P3/2

and must be ac-coupled.

17, 18

LOOUT+,

LOOUT−

Differential LO outputs

The differential output impedance is 50 Ω. These pins

are internally biased and must be ac-coupled. The dc

level varies with LO output drive level. See Table 11.

34, 35

LOIN−,

LOIN+

Differential LO inputs

Differential input impedance of 50 Ω. These pins are

internally biased and must be ac-coupled.

MUXOUT

PLL multiplex output

This output pin provides the PLL reference signal or the

PLL lock detect signal.

VTUNE

VCO tuning voltage

This pin is driven by the output of the loop filter, and the

nominal input voltage range is 1 V to 2.8 V.

RF Inputs

22, 29

RFIN1,

RFIN0

RF inputs

The single-ended RF inputs have a 50 Ω input impedance.

These pins are internally biased to VPOS_5V/2. AC-couple

the RF inputs. Refer to the Layout section for the

recommended printed circuit board (PCB) layout for

improved channel-to-channel isolation. Terminate

unused RF inputs with a dc blocking capacitor to GND

to improve isolation.

RFSW

Pin control of the RF inputs

For RFIN0, set RFSW to logic low, and for RFIN1, set RFSW

to logic high. For logic high, connect this pin to 3.3 V.

Demodulator Outputs

4, 5, 6, 7

I+, I−, Q−,

Q+

I and Q channel mixer baseband outputs

The I and Q mixer outputs have a 50 Ω differential

output impedance (25 Ω per pin). The VOCM pin sets

the output common-mode level.

VOCM

Mixer output common-mode voltage

This input pin sets the common-mode voltage of the I and

Q complex outputs. VOCM needs a clean voltage source

within the 1.5 V to 2.4 V range. Linearity performance

degrades when the voltage is outside this range.

Enable

ENBL

External enable pin control

Set this pin high for enable and low for power-down of

the internal blocks. To specify the internal blocks, write

to Register 0x10, PWRDWN_MSK.

Serial Port Interface

SDIO

SPI data input and output

3.3 V tolerant logic levels.

SCLK

SPI clock

3.3 V tolerant logic levels.

SPI chip select

Active low. 3.3 V tolerant logic levels.

LDO Decoupling

DECL1

Mixer LDO decoupling

Decouple this pin via a 0.22 µF capacitor to ground. Ensure

the decoupling capacitor is located close to the pin.

DECL2

VCO2 LDO decoupling

Decouple this power supply pin via 100 pF and 10 µF

(0805) capacitors to ground. Ensure that the decoupling

capacitors are located close to the pin.

DECL3

VCO LDO decoupling

Decouple this power supply pin via 100 pF and 10 µF

(0805) capacitors to ground. Ensure that the decoupling

capacitors are located close to the pin.

DECL4

2.5V LDO decoupling

Decouple this power supply pin via 100 pF and 10 µF

capacitors to ground. Ensure that the decoupling

capacitors are located close to the pin.

GND

2, 3, 8, 9, 23, 25, 26,

28, 38

GND

Ground

Connect these pins to the GND of the PCB.

EPAD

Exposed pad (EPAD)

The exposed thermal pad is on the bottom of the

package. Solder the exposed pad to ground.

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ADRF6820ACPZ-R7 数据表(PDF) 19 Page - Analog Devices

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