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ADRF6820ACPZ-R7 数据表(PDF) 2 Page - Analog Devices |
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ADRF6820ACPZ-R7 数据表(HTML) 2 Page - Analog Devices |
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2 / 45 page ![]() ADRF6820 Data Sheet Rev. C | Page 2 of 45 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 System Specifications................................................................... 3 Dynamic Performance................................................................. 3 Synthesizer/PLL Specifications................................................... 5 Digital Logic Specifications......................................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 14 RF Input Switch .......................................................................... 14 Tunable Balun ............................................................................. 14 RF Attenuator.............................................................................. 15 LO Generation Block................................................................. 15 Active Mixers .............................................................................. 17 Baseband Buffers........................................................................ 17 Serial Port Interface (SPI) ......................................................... 17 Power Supply Sequencing ......................................................... 17 Applications Information .............................................................. 18 Basic Connections...................................................................... 18 RF Balun Insertion Loss Optimization ................................... 20 Bandwidth Select Modes........................................................... 21 IP3 and Noise Figure Optimization......................................... 23 I/Q Output Loading................................................................... 26 Image Rejection.......................................................................... 27 I/Q Polarity.................................................................................. 28 Layout .......................................................................................... 29 Register Map ................................................................................... 30 Register Address Descriptions.................................................. 31 Outline Dimensions....................................................................... 45 Ordering Guide .......................................................................... 45 REVISION HISTORY 8/2016—Rev. B to Rev. C Changes to Figure 3.......................................................................... 8 Updated Outline Dimensions....................................................... 45 4/2015—Rev. A to Rev. B Changes to Features Section and Figure 1..................................... 1 Changes to Table 1............................................................................ 3 Changes to Figure 3.......................................................................... 8 Changes to Figure 15 and Figure 16............................................. 11 Changes to Figure 25...................................................................... 12 Added Power Supply Sequencing Section................................... 17 Changes to Figure 33 and Table 14............................................... 18 Changes to Figure 38...................................................................... 21 Changes to Figure 51...................................................................... 27 Changes to Address: 0x00, Reset: 0x0000, Name: SOFT_RESET Section.............................................................................................. 31 Changes to Address: 0x33, Reset: 0x0000, Name: MOD_CTL1 Section and Table 31....................................................................... 40 3/2014—Rev. 0 to Rev. A Changes to Features Section ............................................................1 Added LO Harmonic Rejection Parameter and DSA Attenuation Accuracy Parameter, Table 1............................................................3 Changes to Table 2.............................................................................3 Changes to Table 3.............................................................................5 Changes to Figure 5 and Figure 8....................................................9 Changes to Figure 21 and Figure 22 ............................................ 12 Changes to Table 17 ....................................................................... 30 Added Address: 0x44, Reset: 0x0000, Name: DIV_SM_CTL Section and Table 36; Renumbered Sequentially ....................... 43 Changes to Address: 0x45, Reset: 0x0000, Name: VCO_CTL2 Section and Table 37 ...................................................................... 44 Added Address: 0x46, Reset: 0x0000, Name: VCO_RB Section and Table 38 .................................................................................... 44 12/2013—Revision 0: Initial Version |
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