ADRF6820ACPZ-R7 datasheet(26/45 Pages) AD

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ADRF6820

Data Sheet

Rev. C | Page 26 of 45

I/Q OUTPUT LOADING

The I and Q baseband outputs of the ADRF6820 have a 50 Ω

differential impedance. However, voltage gain and linearity

performance are optimized with the use of a 200 Ω differential

load. This may not be the most favorable termination for every

application; therefore, performance trade-offs can be made for

lower output loads.

The output load on the differential I/Q outputs has a direct

impact on the voltage gain where the gain decreases with lighter

loads. The 50 Ω differential source impedance (RS) of the

ADRF6820 forms a voltage divider with the external load

resistor (RL). The performance of the ADRF6820 was optimized

for and specified with a differential load termination of 200 Ω.

For a 200 Ω differential load termination, the voltage divider

ratio is given by

VOUT/VIN = RL/(RL + RS)

where RS = 50 Ω.

The change in gain due to different load impedance is given by

(

)

(

)

Gain

)

(

)

(

where:

RL1 = 200 Ω.

RL2 is the new load impedance.

The conversion gain of the ADRF6820 at fRF = 2100 MHz and

fIF = 200 MHz is −3.2 dB. For the same test conditions with a

100 Ω load, the gain decreases by 20log(5/6) = −1.58 dB to a

voltage gain of −4.6 dB. Figure 47 shows the voltage gain vs. IF

frequency for fLO = 1840 MHz and BWSEL = 2 for common

output loads.

–13

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

IF FREQUENCY (MHz)

RL = 100Ω

RL = 200Ω

RL = 50Ω

Figure 47. Voltage Gain vs. IF Frequency for LO = 1840 MHz, BWSEL = 2

In addition to the lower conversion gain, the effect of lower

output load impedance is degraded linearity performance.

The degraded performance is a result of the emitter follower

buffers, after the mixers, needing to deliver more load current;

therefore, they operate closer to their nonlinear region. To

improve performance with lighter loads, such as 50 Ω, increase

the bias current of the emitter follower by increasing BB_BIAS

(Register 0x34, Bits[11:10]) to its maximum of 13.5 mA. Refer

to Table 13 for the bias current settings.

IF FREQUENCY (MHz)

IIP3 = 50

Ω

IIP3 = 100

Ω

IIP3 = 200

Ω

IIP2 = 50

Ω

IIP2 = 100

Ω

IIP2 = 200

Ω

Figure 48. IIP3 and IIP2 vs. IF Frequency for fLO = 1840 MHz and BWSEL = 2

Figure 48 shows input IP3 and input IP2 performance vs. IF

frequency for 50 Ω, 100 Ω, and 200 Ω loads. For the 100 Ω and

200 Ω load impedance, the bias current was configured to its

default of 9 mA, whereas for the 50 Ω load, the current was

increased to the maximum to achieve the same level of input

IP3 performance as the higher output loads.

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