ADRF6820ACPZ-R7 datasheet(14/45 Pages) AD

14 / 45 page

ADRF6820

Data Sheet

Rev. C | Page 14 of 45

THEORY OF OPERATION

The ADRF6820 integrates many of the essential building blocks

for a high bandwidth quadrature demodulator and receiver,

especially for the feedback downconverter path for the digital

predistortion in cellular base stations. The main features include a

single pole, double throw (SPDT) RF input switch, a variable RF

attenuator, a tunable balun, a pair of active mixers, and two

baseband buffers. Additionally, the local oscillator (LO) signals for

the mixers are generated by a fractional-N synthesizer and a

multicore voltage controlled oscillator (VCO), covering an octave

frequency range with low phase noise. A pair of flip-flops then

divides the LO frequency by two and generates the in-phase and

quadrature phase LO signals to drive the mixers. The synthesizer

uses a fractional-N phase-locked loop (PLL) with additional

frequency dividers to enable continuous LO coverage from

356.25 MHz to 2850 MHz. Alternatively, a polyphase phase splitter

is also available to generate LO signals in quadrature from an

external LO source.

Putting all the building blocks of the ADRF6820 together, the

signal path through the device starts at one of two RF inputs

selected by the input multiplexer (mux) and is converted to a

differential signal via a tunable balun. The differential RF signal

is attenuated to an optimal input level via the digital step attenuator

with 15 dB of attenuation range in 1 dB steps. The RF signal is

then mixed with the LO signal in the Gilbert cell mixers down

to an intermediate frequency (IF) or baseband. The emitter

followers further buffer the outputs of the mixers with an

adjustable output common-mode level.

The different sections of the ADRF6820 are controlled through

registers programmable via a serial port interface (SPI).

RF INPUT SWITCH

The ADRF6820 integrates a SPDT switch where one of two RF

inputs is selected. Selection of the desired RF input is achieved

externally via a control pin or serially via register writes to the

SPI. When compared to the serial write approach, pin control

allows faster switching between the RF inputs. Using the RFSW

pin (Pin 20), the RF input can switch within 100 ns. When serial

port control is used, the switching time is dominated by the latency

of the SPI programming, which is 2.4 µs minimum for a 10 MHz

serial clock.

The RFSW_MUX bit (Register 0x23, Bit 11) selects whether the

RF input switch is controlled via the external pins or via the SPI

(see Table 8). By default at power-up, the device is configured for

pin control. Connecting RFSW to GND selects RFIN0, and

connecting RFSW to VPOS_3P3 selects RFIN1. In serial mode

control, writing to the RFSW_SEL bit (Register 0x23, Bit 9)

allows selection of one of the two RF inputs. If only one RFINx port

is used, the unused RF input must be properly terminated to

improve isolation. The RFIN0/REFIN1 ports are internally

terminated with 50 Ω resistors, and the dc level is 2.5 V. To avoid

disrupting the dc level, the recommended termination is a dc

blocking capacitor to GND. Figure 30 shows the recommended

configuration when only RFIN0 is selected.

RFIN0

RFIN1

Ω

0.1µF

Figure 30. Terminating Unused RF Input Ports

TUNABLE BALUN

The ADRF6820 integrates a programmable balun operating

over a 695 MHz to 2700 MHz frequency range. The tunable

balun offers the benefit of ease of drivability with single-ended,

50 Ω RF inputs, and the single-ended-to-differential conversion

of the integrated balun provides additional common-mode

noise rejection.

BAL_COUT

REG 0x30[7:5]

BAL_CIN

REG 0x30[3:1]

RFINx

Figure 31. Integrated Tunable Balun

To accomplish RF balun tuning, switch the parallel capacitances

on the primary and secondary sides of the balun by writing to

windings of the balun changes the resonant frequency of the

inductor capacitor (LC) tank. Therefore, selecting the proper

combination of BAL_CIN (Register 0x30, Bits[3:1]) and

BAL_COUT (Register 0x30, Bits[7:5]) sets the desired frequency

and optimizes gain. Under most circumstances, the input and

output capacitances are tuned together; however, sometimes for

matching reasons, it is advantageous to tune them independently.

Table 8. RF Input Selection Table

RFSW_MUX (Register 0x23, Bit 11)

RFSW_SEL SPI Control (Register 0x23, Bit 9)

RFSW Pin Control (Pin 20)

RF Input

RFIN0

RFIN1

RFIN0

RFIN1

X = don’t care.

ADRF6820ACPZ-R7 数据表(PDF) 14 Page - Analog Devices

ADRF6820ACPZ-R7 数据表(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载

链接网址

ADRF6820ACPZ-R7 数据表(PDF) 14 Page - Analog Devices

ADRF6820ACPZ-R7 数据表(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表 下载

链接网址

数据表下载