Data Sheet

ADRF6820

Rev. C | Page 5 of 45

SYNTHESIZER/PLL SPECIFICATIONS

bandwidth = 20 kHz, measured at LO output, unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

PLL REFERENCE

Frequency

12

320

MHz

Amplitude

4

14

dBm

PFD = 30.72 MHz

468.76

Hz

PFD = 30.72 MHz, charge pump = 500 µA,

loop bandwidth = 40 kHz, antibacklash delay = 0.5 ns,

charge pump bleed current = 78.125 µA down

5

ms

PFD FREQUENCY

24

40

MHz

INTERNAL VCO RANGE

2850

5700

MHz

REFERENCE SPURS

<−100

dBc

<−100

dBc

−90.67

dBc

−95

dBc

−97

dBc

<−100

dBc

<−100

dBc

1 kHz to 40 MHz integration bandwidth, PFD = 38.4 MHz,

loop bandwidth = 20 kHz, antibacklash delay = 0 ns,

charge pump bleed current = 46.8 µA down,

LO frequency = 1562.5 MHz

0.6

°rms

CLOSED-LOOP PERFORMANCE

20 kHz Loop Filter

10 kHz offset

−94.7

dBc/Hz

20 kHz offset

−95.8

dBc/Hz

100 kHz offset

−113

dBc/Hz

200 kHz offset

−122.4

dBc/Hz

600 kHz offset

−136.5

dBc/Hz

1 MHz offset

−141.5

dBc/Hz

10 MHz offset

−153.3

dBc/Hz

40 MHz offset

−154.6

dBc/Hz

1

2

Lock time is defined as the time it takes from the end of a register write for a change in frequency to the point where the frequency of the output is within 500 Hz of

the intended frequency.

3

Measured with a nominal device with normal supply and temperature.