ADRF6820ACPZ-R7 datasheet(17/45 Pages) AD

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Data Sheet

ADRF6820

Rev. C | Page 17 of 45

Required PLL/VCO Settings and Register Write Sequence

In addition to writing to the necessary registers to configure the

PLL and VCO for the desired LO frequency and phase noise

performance, the registers in Table 12 are required register writes.

To ensure that the PLL locks to the desired frequency, follow the

proper write sequence of the PLL registers. Configure the PLL

registers accordingly to achieve the desired frequency, and the

last writes must be to Register 0x02 (INT_DIV), Register 0x03

(FRAC_DIV), or Register 0x04 (MOD_DIV). When Register 0x02,

VCO calibration initiates, which is the last step to locking the PLL.

Table 12. Required PLL/VCO Register Writes

Address[Bits]

Bit Name

Setting

Description

0x21[3]

PFD_POLARITY

0x1

Negative polarity

0x49[15:0]

RESERVED,

SET_1, SET_0

0x14B4

Internal settings

ACTIVE MIXERS

The signal from the RFDSA is split to drive a pair of double

balanced, Gilbert cell active mixers, to be downconverted by the

LO signals to baseband. Program the current in the mixers by

changing the value of the MIX_BIAS bits (Register 0x31,

Bits[12:10]) for trade-off between output noise and linearity.

The active mixers employ a distortion correction circuit for

cancelling the third-order distortions coming from the mixers.

Determine the amplitude and phase of the correction signals by

the combination of control register entries DEMOD_RDAC and

DEMOD_CDAC (Register 0x31, Bits[8:5] and Register 0x31,

Bits[3:0], respectively). Refer to the IP3 and Noise Figure

Optimization section for more information.

Demodulator gain and bandwidth are set by the resistance and

capacitance in the mixer loads, which are controlled by the

BWSEL bits (Register 0x34, Bits[9:8]) according to Table 15. Refer

to the Bandwidth Select Modes section for more information.

BASEBAND BUFFERS

Emitter followers buffer the signals at the mixer loads and drive

the baseband output pins (I+, I−, Q−, and Q+). Bias currents of

the emitter followers are controlled by the BB_BIAS bits

(Register 0x34, Bits[11:10]), as shown in Table 13. Set the bias

current according to the load driving capabilities needed (that

is, BB_BIAS = 1 for the specified 200 Ω load, and BB_BIAS = 2

for the 50 Ω or 100 Ω loads are recommended). The differential

impedance of the baseband outputs is 50 Ω; however, the

ADRF6820 output load must be high (that is, 200 Ω) for

optimized linearity performance. Refer to the I/Q Output

Loading section for supporting data.

Table 13. Baseband Buffer Bias

BB_BIAS (Register 0x34, Bits[11:10])

Bias Current (mA)

4.5

13.5

SERIAL PORT INTERFACE (SPI)

The SPI of the ADRF6820 allows the user to configure the device

for specific functions or operations through a structured register

space provided inside the chip. This interface provides users with

added flexibility and customization. Addresses are accessed via

the serial port interface and can be written to or read from the

serial port interface.

The serial port interface consists of three control lines: SCLK,

SDIO, and CS. SCLK (serial clock) is the serial shift clock, and it

synchronizes the serial interface reads and writes. SDIO is the

serial data input or the serial data output depending on the

instruction sent and the relative position in the timing frame.

CS (chip select bar) is an active low control that gates the read

and write cycles. The falling edge of CS in conjunction with the

rising edge of SCLK determines the start of the frame. When CS

is high, all SCLK and SDIO activity is ignored. See Table 4 for

the serial timing and its definitions.

The ADRF6820 protocol consists of 7 register address bits,

followed by a read/write and 16 data bits. Both the address and

data fields are organized with the most significant bit (MSB)

first and end with the least significant bit (LSB).

On a write cycle, up to 16 bits of serial write data is shifted in,

MSB to LSB. If the rising edge of CS occurs before the LSB of

the serial data is latched, only the bits that were latched are

written to the device. If more than 16 data bits are shifted in, the

16 most recent bits are written to the device. The ADRF6820

input logic level for the write cycle supports an interface as low

as 1.8 V.

On a read cycle, up to 16 bits of serial read data is shifted out,

MSB first. Data shifted out beyond 16 bits is undefined. Read

back content at a given register address does not necessarily

correspond with the write data of the same address. The output

logic level for a read cycle is 2.5 V.

POWER SUPPLY SEQUENCING

The ADRF6820 operates from two nominal supply voltages,

3.3 V and 5 V. Careful consideration must be exercised to

ensure that the voltage on all pins connected to VPOS_3P3

never exceed the voltage on all pins connected to VPOS_5V.

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