ADRF6820ACPZ-R7 datasheet(16/45 Pages) AD

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ADRF6820

Data Sheet

Rev. C | Page 16 of 45

LO Frequency and Dividers

The signal coming from the VCO or the external LO inputs

goes through a series of dividers before it is buffered to drive

the active mixers. Two programmable divide-by-two stages

divide the frequency of the incoming signal by 1, 2, or 4 before

reaching the quadrature divider that further divides the signal

frequency by 2 to generate the in-phase and quadrature-phase

LO signals for the mixers. The control bits (Register 0x22,

Bits[4:3]) needed to select the different LO frequency ranges

are listed in Table 10.

Table 10. LO Frequency and Dividers

LO Frequency

Range (MHz)

fVCO/fLO or

fEXTLO/fLO

DIV8_EN

(Register 0x22,

Bit 4)

DIV4_EN

(Register 0x22,

Bit 3)

1425 to 2850

712.5 to 1425

356.25 to 712.5

PLL Frequency Programming

The N divider divides down the differential VCO signal to the

PFD frequency. The N divider can be configured for fractional or

integer mode by addressing the DIV_MODE bit (Register 0x02,

Bit 11). The default configuration is set for fractional mode. Use

the following equations to determine the N value and PLL

frequency:

VCO

PFD

MOD

FRAC

INT

LO_DIVIDER

PFD

where:

fPFD is the phase frequency detector frequency.

fVCO is the VCO frequency.

N is the fractional divide ratio (INT + FRAC/MOD).

INT is the integer divide ratio programmed in Register 0x02.

FRAC is the fractional divider programmed in Register 0x03.

MOD is the modulus divide ratio programmed in Register 0x04.

fLO is the LO frequency going to the mixer core when the loop is

locked.

LO_DIVIDER is the final frequency divider ratio that divides

the frequency of the VCO or the external LO signal down by 2,

4, or 8 before it reaches the mixer, as shown in Table 10.

PLL Lock Time

The time it takes to lock the PLL after the last register is written

breaks down into two parts: VCO band calibration and loop

settling.

After writing to the last register, the PLL automatically performs

a VCO band calibration to choose the correct VCO band. This

calibration takes approximately 94,208 PFD cycles. For a 40 MHz

fPFD, this corresponds to 2.36 ms. After calibration completes,

the feedback action of the PLL causes the VCO to lock to the

correct frequency eventually. The speed with which this lock

occurs depends on the nonlinear cycle slipping behavior, as well

as the small signal settling of the loop. For an accurate estimation

of the lock time, download the ADIsimPLL tool to capture these

effects correctly. In general, higher bandwidth loops tend to

lock more quickly than lower bandwidth loops.

The lock detect signal is available as one of the selectable outputs

through the MUXOUT pin, with a logic high signifying that the

loop is locked. The control for the MUXOUT pin is located in

the REF_MUX_SEL bits (Register 0x21, Bits[6:4]), and the

default configuration is for PLL lock detect.

Buffered LO Outputs

A buffered version of the internal LO signal is available

differentially at the LOOUT+ and LOOUT− pins (Pin 17 and

Pin 18). When the quadrature LO signals are generated using

the quadrature divider, the output signal is available at either 2×

or 1× the frequency of the LO signal at the mixer. Set the output

to different drive levels by accessing the LO_DRV_LVL bits

(Register 0x22, Bits[7:6]), as shown in Table 11.

The availability of the LO signal makes it possible to daisy-chain

many devices synchronously. One ADRF6820 device can serve

as the master where the LO signal is sourced, and the subsequent

slave devices share the same LO output signal from the master.

This flexibility substantially eases the LO requirements of a

system requiring multiple LOs.

Table 11. LO Output Level

LO_DRV_LVL

(Register 0x22, Bits[7:6])

Amplitude (dBm)

DC Level (V)

−5

3.0

−1

2.85

2.7

2.5

External LO Mode

Use the VCO_SEL bits (Register 0x22, Bits[2:0]) to select external

or internal LO mode. To configure for external LO mode, set

signals to Pin 34 (LOIN−) and Pin 35 (LOIN+). The external LO

frequency range is 350 MHz to 6 GHz. When the polyphase phase

splitter is selected, a 1× LO signal is required for the active mixer,

or a 2× LO signal can be used with the internal quadrature

divider, as shown in Table 9.

The LOIN+ and LOIN− input pins must be ac-coupled. When

not in use, leave the LOIN+ and LOIN− pins unconnected.

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