LSM303D datasheet(22/52 Pages) STMICROELECTRONICS

22 / 52 page

Digital interfaces

LSM303D

22/52

DocID023312 Rev 2

6.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a high-to-low transition on the data line while the SCL line is held high. After this

has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the START condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a START condition with its address. If they match, the device considers itself

addressed by the master.

The slave address (SAD) associated to the LSM303D is 00111xxb, whereas the xx bits are

modified by the SDO/SA0 pin in order to modify the device address. If the SDO/SA0 pin is

connected to the voltage supply, the address is 0011101b, otherwise, if the SDO/SA0 pin is

connected to ground, the address is 0011110b. This solution permits the connection and

addressing of two different accelerometers to the same I2C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line low so that it

remains stable low during the high period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded in the LSM303D behaves as a slave device and the following protocol

must be adhered to. After the START condition (ST) a slave address is sent, once a slave

acknowledge (SAK) has been returned, an 8-bit sub-address is transmitted: the 7 LSb

represent the actual register address while the MSb enables address auto-increment. If the

MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow

multiple data read/write.

The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write)

the master transmits to the slave with direction unchanged. Table 11 explains how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 11. SAD+read/write patterns

Command

SDO/SA0 pin

SAD[6:2]

SAD[1:0]

R/W

SAD+R/W

Read

00111

Write

00111

Read

00111

Write

00111

Table 12. Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

LSM303D 数据表(PDF) 22 Page - STMicroelectronics

LSM303D 数据表(HTML) 22 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

数据表下载

链接网址

LSM303D 数据表(PDF) 22 Page - STMicroelectronics

LSM303D 数据表(HTML) 22 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

数据表 下载

链接网址

数据表下载