LSM303D datasheet(43/52 Pages) STMICROELECTRONICS

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LSM303D

Reading at this address clears the IG_SRC1 (31h) IA bit (and the interrupt signal on the

corresponding interrupt pin) and allows the refreshment of data in the IG_SRC1 (31h)

8.32

IG_THS1 (32h)

8.33

IG_DUR1 (33h)

The D6 - D0 bits set the minimum duration of the interrupt 1 event to be recognized.

Duration steps and maximum values depend on the ODR chosen.

Table 66. IG_SRC1 register description

Interrupt status. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt; 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt; 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt; 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt; 1: X high event has occurred)

X low. Default value: 0

(0: no interrupt; 1: X low event has occurred)

Table 67. IG_THS1 register

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 68. IG_THS1 register description

THS[6:0]

Interrupt generator 1 threshold. Default value: 000 0000

Table 69. IG1_DUR1 register

D6D5D4D3D2D1D0

Table 70. IG1_DUR1 register description

D[6:0]

Duration value. Default value: 000 0000

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