LSM303D datasheet(41/52 Pages) STMICROELECTRONICS

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LSM303D

Interrupt generator 2 can change the FIFO mode.

8.29

FIFO_SRC (2Fh)

FiFO status register.

8.30

IG_CFG1 (30h)

Inertial interrupt generator 1 configuration register.

Table 59. FIFO mode configuration

FM2

FM1

FM0

FIFO mode

Bypass mode

FIFO mode

Stream mode

Stream-to-FIFO mode

Bypass-to-Stream mode

Table 60. FIFO_SRC register

FTH

OVRN

EMPTY

FSS4

FSS3

FSS2

FSS1

FSS0

Table 61. FIFO_SRC register description

FTH

FIFO threshold status.

FTH bit is set to ‘1’ when FIFO content exceeds threshold level.

OVRN

FIFO overrun status.

OVRN bit is set to ‘1’ when FIFO buffer is full.

EMPTY

Empty status.

EMPTY bit is set to ‘1’ when all FIFO samples have been read and FIFO is empty.

FSS[4:0]

FIFO stored data level.

FSS4-0 bits contain the current number of unread FIFO levels.

Table 62. IG_CFG1 register

AOI

ZHIE/

ZUPE

ZLIE/

ZDOWNE

YHIE/

YUPE

YLIE/

YDOWNE

XHIE/

XUPE

XLIE/

XDOWNE

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