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STM32F100RC 数据表(PDF) 55 Page - STMicroelectronics

部件名 STM32F100RC
功能描述  Clock, reset and supply management
PDF  106 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F100RC 数据表(HTML) 55 Page - STMicroelectronics

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STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
105
Wakeup time from low-power mode
The wakeup times given in Table 26 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under the ambient temperature and VDD supply
voltage conditions summarized in Table 9.
5.3.8
PLL characteristics
The parameters given in Table 27 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 26. Low-power mode wakeup timings
Symbol
Parameter
Typ
Unit
tWUSLEEP(1)
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
Wakeup from Sleep mode
1.8
µs
tWUSTOP(1)
Wakeup from Stop mode (regulator in run mode)
3.6
µs
Wakeup from Stop mode (regulator in low-power mode)
5.4
tWUSTDBY(1)
Wakeup from Standby mode
50
µs
Table 27. PLL characteristics
Symbol
Parameter
Value
Unit
Min(1)
Typ
Max(1)
1. Based on device characterization, not tested in production.
fPLL_IN
PLL input clock(2)
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
18.0
24
MHz
PLL input clock duty cycle
40
-
60
%
fPLL_OUT
PLL multiplier output clock
16
-
24
MHz
tLOCK
PLL lock time
-
-
200
µs
Jitter
Cycle-to-cycle jitter
-
-
300
ps



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