STM32F100RC datasheet(89/106 Pages) STMICROELECTRONICS

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STM32F100xC, STM32F100xD, STM32F100xE

Electrical characteristics

105

Figure 37. 12-bit buffered /non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external

loads directly without the use of an external operational amplifier. The buffer can be bypassed by

configuring the BOFFx bit in the DAC_CR register.

Offset(1)

Offset error

(difference between measured value

at Code (0x800) and the ideal value =

VREF+/2)

±10

Given for the DAC in 12-bit

configuration

±3

LSB

Given for the DAC in 10-bit at

VREF+ = 3.6 V

±12

LSB

Given for the DAC in 12-bit at

VREF+ = 3.6 V

Gain

error(1)

Gain error

±0.5

Given for the DAC in 12-bit

configuration

tSETTLING(1)

Settling time (full scale: for a 10-bit

input code transition between the

lowest and the highest input codes

when DAC_OUT reaches final value

±1LSB

-3

µs

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

Update

rate(1)

Max frequency for a correct

DAC_OUT change when small

variation in the input code (from code i

to i+1LSB)

MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

tWAKEUP(1)

Wakeup time from off state (Setting

the ENx bit in the DAC Control

6.5

µs

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

input code between lowest and

highest possible ones.

PSRR+ (1)

Power supply rejection ratio (to VDDA)

(static DC measurement

–67

–40

No RLOAD, CLOAD = 50 pF

1. Preliminary values.

2. Quiescent mode refer to the state of the DAC keeping steady value on the output, so no dynamic consumption is involved.

Table 55. DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max(1) Unit

Comments

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