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STM32F100RC 数据表(PDF) 84 Page - STMicroelectronics |
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STM32F100RC 数据表(HTML) 84 Page - STMicroelectronics |
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84 / 106 page  R AIN T S f ADC C ADC 2 N2 + () ln × × ---------------------------------------------------------------- R ADC – < Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE 84/106 DocID15081 Rev 10 Equation 1: RAIN max formula: The above formula (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 51. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply - 2.4 - 3.6 V VREF+ Positive reference voltage - 2.4 - VDDA V IVREF Current on the VREF input pin - - 160(1) 220(1) µA fADC ADC clock frequency - 0.6 - 12 MHz fS(2) Sampling rate - 0.05 - 1 MHz fTRIG(2) External trigger frequency fADC = 12 MHz - - 823 kHz -- - 17 1/fADC VAIN(3) Conversion voltage range - 0 (VSSA tied to ground) -VREF+ V RAIN(2) External input impedance See Equation 1 and Table 52 for details -- 50 k Ω RADC(2) Sampling switch resistance - - - 1 k Ω CADC(2) Internal sample and hold capacitor -- - 8 pF tCAL(2) Calibration time fADC = 12 MHz 5.9 µs -83 1/fADC tlat(2) Injection trigger conversion latency fADC = 12 MHz - - 0.214 µs -- - 3(4) 1/fADC tlatr(2) Regular trigger conversion latency fADC = 12 MHz - - 0.143 µs -- - 2(4) 1/fADC tS(2) Sampling time fADC = 12 MHz 0.125 - 17.1 µs 1.5 - 239.5 1/fADC tSTAB(2) Power-up time - 0 0 1 µs tCONV(2) Total conversion time (including sampling time) fADC = 12 MHz 1.17 - 21 µs - 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. Preliminary values. 2. Guaranteed by design, not tested in production. 3. VREF+ is internally connected to VDDA 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 51. |
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