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STM32F100RC 数据表(PDF) 78 Page - STMicroelectronics

部件名 STM32F100RC
功能描述  Clock, reset and supply management
PDF  106 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F100RC 数据表(HTML) 78 Page - STMicroelectronics

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Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
78/106
DocID15081 Rev 10
5.3.16
TIMx characteristics
The parameters given in Table 47 are guaranteed by design.
Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
5.3.17
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 48 are preliminary values derived
from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply
voltage conditions summarized in Table 9.
The STM32F100xx value line I2C interface meets the requirements of the standard I2C
communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 48. Refer also to Section 5.3.13: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
Table 47. TIMx characteristics
Symbol
Parameter
Conditions(1)
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM5, TIM15, TIM16 and TIM17
timers.
Min
Max
Unit
tres(TIM)
Timer resolution time
-1
-
tTIMxCLK
fTIMxCLK = 24 MHz 41.7
-
ns
fEXT
Timer external clock
frequency on CHx(2)
2. CHx is used as a general term to refer to CH1 to CH4 for TIM1, TIM2, TIM3, TIM4 and TIM5, to the CH1 to
CH2 for TIM15, and to CH1 for TIM16 and TIM17.
0fTIMxCLK/2
MHz
fTIMxCLK = 24 MHz
0
12
MHz
ResTIM
Timer resolution
-
-
16
bit
tCOUNTER
16-bit counter clock period
when the internal clock is
selected
-
1
65536
tTIMxCLK
fTIMxCLK = 24 MHz
-
2730
µs
tMAX_COUNT Maximum possible count
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 24 MHz
-
178
s



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