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STM32F100RC 数据表(PDF) 61 Page - STMicroelectronics |
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STM32F100RC 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 106 page  DocID15081 Rev 10 61/106 STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics 105 Figure 18. Asynchronous multiplexed PSRAM/NOR write waveforms Table 33. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) 1. CL = 15 pF. 2. Preliminary values. Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 5THCLK – 1 5THCLK + 2 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low 2THCLK 2THCLK + 1 ns tw(NWE) FSMC_NWE low time 2THCLK – 1 2THCLK + 2 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK – 1 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 7 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 3 5 ns tw(NADV) FSMC_NADV low time THCLK – 1 THCLK + 1 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high THCLK – 3 - ns th(A_NWE) Address hold time after FSMC_NWE high 4THCLK -ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.6 ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK – 1.5 - ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK + 1.5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK – 5 - ns |
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