MB96F348CWCPMC-GSE2 datasheet(56/109 Pages) CYPRESS

56 / 109 page

MB96340 Series

Document Number: 002-04579 Rev. *A

Page 56 of 109

13.3.1 Single phase external clock

■ When using a single phase external clock, X0 pin must be driven and X1 pin left open.

13.3.2 Opposite phase external clock

■ When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the

X0 (X0A) pins.

13.4

Unused sub clock signal

If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin

must be left open.

13.5

Notes on PLL clock mode operation

If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts

to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.

13.6

Power supply pins (VCC/VSS)

It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or

VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.

VCC and VSS must be connected to the device from the power supply with lowest possible impedance.

As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1

F between VCC and VSS as close

as possible to VCC and VSS pins.

MB96F348CWCPMC-GSE2 数据表(PDF) 56 Page - Cypress Semiconductor