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MB96F348CWCPMC-GSE2 数据表(PDF) 70 Page - Cypress Semiconductor |
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MB96F348CWCPMC-GSE2 数据表(HTML) 70 Page - Cypress Semiconductor |
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70 / 109 page  MB96340 Series Document Number: 002-04579 Rev. *A Page 70 of 109 14.4 AC Characteristics 14.4.1 Source Clock timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Value Unit Remarks Min Typ Max Clock frequency fC X0, X1 3 - 16 MHz When using a crystal oscillator, PLL off 0- 16 MHz When using an opposite phase external clock, PLL off 3.5 - 16 MHz When using a crystal oscillator or opposite phase external clock, PLL on Clock frequency fFCI X0 0- 56 MHz When using a single phase external clock in “Fast Clock Input mode” (not available in MB96F34xY/R/AxA), PLL off 3.5 - 56 MHz When using a single phase external clock in “Fast Clock Input mode” (not available in MB96F34xY/R/AxA), PLL on Clock frequency fCL X0A, X1A 32 32.768 100 kHz When using an oscillation circuit 0 - 100 kHz When using an opposite phase external clock X0A 0 - 50 kHz When using a single phase external clock Clock frequency fCR - 50 100 200 kHz When using slow frequency of RC oscillator 1 2 4 MHz When using fast frequency of RC oscillator PLL Clock frequency fCLKVCO - 64 - 200 MHz Permitted VCO output frequency of PLL (CLKVCO) PLL Phase Jitter TPSKEW -- - 5 ns For CLKMC (PLL input clock) MHz Input clock pulse width PWH, PWL X0,X1 8 - - ns Duty ratio is about 30% to 70% Input clock pulse width PWHL, PWLL X0A,X1A 5 - - s X0 tCYL PWH PWL VIL VIH X0A tCYLL PWH PWLL VIL VIH |
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