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MB96F348CWCPMC-GSE2 数据表(PDF) 100 Page - Cypress Semiconductor |
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MB96F348CWCPMC-GSE2 数据表(HTML) 100 Page - Cypress Semiconductor |
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100 / 109 page  MB96340 Series Document Number: 002-04579 Rev. *A Page 100 of 109 Timer mode PLL CLKMC = 4 MHz, CLKPLL = 56 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.9 V Main osc. CLKMC = 4 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V RC clock fast CLKRC = 2 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V RC clock slow CLKRC = 100 kHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V Sub osc. CLKSC = 100 kHz (System clocks are stopped in this mode) Regulator in Low Power Mode A, Core Voltage = 1.8 V Stop mode stopped (All clocks are stopped in this mode) Regulator in Low Power Mode B, Core Voltage = 1.8 V Table 6: Used settings Mode Selected Source Clock Clock/Regulator Settings |
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