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MB96F348CWCPMC-GSE2 数据表(PDF) 87 Page - Cypress Semiconductor |
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MB96F348CWCPMC-GSE2 数据表(HTML) 87 Page - Cypress Semiconductor |
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87 / 109 page  MB96340 Series Document Number: 002-04579 Rev. *A Page 87 of 109 14.4.13 I2C Timing [1] : R,C: Pull-up resistor and load capacitor of the SCL and SDA lines. [2]: The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. [3] : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT≥ 250 ns must then be met. [4] : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz. (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V) Parameter Symbol Condition Standard-mode Fast-mode[4] Unit Min Max Min Max SCL clock frequency fSCL R 1.7 k, C 50 pF[1] 0 100 0 400 kHz Hold time (repeated) START condition SDA↓→SCL tHDSTA 4.0 - 0.6 - s “L” width of the SCL clock tLOW 4.7 - 1.3 - s “H” width of the SCL clock tHIGH 4.0 - 0.6 - s Set-up time for a repeated START condition SCL↓→SDA↑ tSUSTA 4.7 - 0.6 - s Data hold timeSCL↑→SDA↑↓ tHDDAT 03.45[2] 00.9[3] s Data set-up timeSDA↑↓→SCL↑ tSUDAT 250 - 100 - ns Set-up time for STOP conditionSCL↑→SDA↑ tSUSTO 4.0 - 0.6 - s Bus free time between a STOP and START condition tBUS 4.7 - 1.3 - s SDA SCL tLOW tSUDAT tHDSTA tBUS tHDSTA tHDDAT tHIGH tSUSTA tSUSTO |
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