MB96F348CWCPMC-GSE2 datasheet(8/109 Pages) CYPRESS

8 / 109 page

MB96340 Series

Document Number: 002-04579 Rev. *A

Page 8 of 109

2. Block Diagram

Figure 1. Block diagram of MB96(F)34x

Flash Memory B

or Data Flash A [2]

I2C

2 ch.

SDA0, SDA1

SCL0, SCL1

DMA

Controller

Boot ROM

Peripheral

Bus Bridge

Peripheral

Bus Bridge

16FX Core Bus (CLKB)

USART

7 ch.

10-bit ADC

24 ch.

Alarm

Comparator

2 ch. *4

16-bit Reload

Timer

4 ch.

I/O Timer 0

ICU 0/1/2/3

OCU 0/1/2/3

16-bit PPG

16 ch.

CAN

Interface

2 ch.

External

Interrupt

Real Time

Clock

Watchdog

RAM

Voltage

Regulator

SIN0...SIN3, SIN2_R, SIN7_R...SIN9_R

SOT0...SOT3, SOT2_R, SOT7_R...SOT9_R

SCK0...SCK3, SCK2_R, SCK7_R...SCK9_R

ALARM0 [4]

ALARM1 [4]

WOT

AVCC

AVSS

AVRH

AVRL/AVRH2 [5]

AN0 ... AN23

ADTG, ADTG_R

TIN0 ... TIN3

TOT0 ... TOT3

FRCK0

IN0 ... IN3

OUT0 ... OUT3

INT0 ... INT15

TX0, TX1 [3]

RX0, RX1 [3]

VCC

VSS

PPG0 ... PPG15

TTG0 ... TTG15

I/O Timer 1

ICU 4/5/6/7

OCU 4/5/6/7

FRCK1

IN4 ... IN7

OUT4 ... OUT7

16FX

CPU

Interrupt

Controller

Clock &

Mode Controller

Flash

Memory A

Memory Patch

Unit

AD00 ... AD15

A16 ... A23

ALE

RDX

WR(L)X, WRHX

HRQ

HAKX

RDY

ECLK

External Bus

Interface

LBX, UBX

CS0 ... CS5

NMI, NMI_R

[2]: Flash B only available on MB96F34xCyy, MB96F34xHyy or MB96F34xTyy

INT0_R ... INT2_R

INT3_R1

CKOT0, CKOT1

CKOTX0, CKOTX1

X0, X1

X0A, X1A [1]

RSTX

MD0...MD2

INT4_R, INT5_R

INT7_R ... INT15_R

[1]: X0A, X1A only available on MB96(F)34xyWy

[3]: CAN interfaces are not available on MB96(F)34xAyy or MB96(F)34xCyy

RLT6

Data Flash A only available on MB96F34xDyy or MB96F34xFyy

CAN1 is not available on MB96F345Dyy or MB96F345Fyy

[4]: Alarm comparator is not available on MB96F345Dyy or MB96F345Fyy

[5]: A/D converter reference voltage switch is not available on MB96F345Dyy or MB96F345Fyy

MB96F348CWCPMC-GSE2 数据表(PDF) 8 Page - Cypress Semiconductor

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