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MB96F348CWCPMC-GSE2 数据表(PDF) 81 Page - Cypress Semiconductor

部件名 MB96F348CWCPMC-GSE2
功能描述  8-byte instruction execution queue
PDF  109 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB96F348CWCPMC-GSE2 数据表(HTML) 81 Page - Cypress Semiconductor

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MB96340 Series
Document Number: 002-04579 Rev. *A
Page 81 of 109
14.4.9 Bus Timing (Write)
(TA  40°C to 125°C, VCC  5.0 V  10, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Condition
Value
Unit
Remarks
Min
Max
Valid address
 WRX  time
tAVWL
WRX, WRLX,
WRHX, A[23:16]
EACL:ACE=0
3tCYC/2  15
-
ns
EACL:ACE=1
5tCYC/2  15
-
tADVWL
WRX, WRLX,
WRHX, AD[15:0]
EACL:ACE=0
tCYC  15
-
ns
EACL:ACE=1
2tCYC  15
-
WRX pulse width
tWLWH
WRX, WRXL,
WRHX
-tCYC  5-
ns
w/o cycle
extension
Valid data output
 WRX 
time
tDVWH
WRX, WRLX,
WRHX, AD[15:0]
-tCYC  20
-
ns
w/o cycle
extension
WRX
  Data hold time
tWHDX
WRX, WRLX,
WRHX, AD[15:0]
-tCYC/2  15
-
ns
WRX
  Address valid time
tWHAX
WRX, WRLX,
WRHX, A[23:16]
-
tCYC/2  15
-
ns
WRX
  ALE  time
tWHLH
WRX, WRLX,
WRHX, ALE
EBM:ACE=1 and
EACL:STS=1
2tCYC  10
-
ns
other EBM:ACE and
EACL:STS setting
tCYC  10
-
WRX
  ECLK  time
tWLCH
WRX, WRLX,
WRHX, ECLK
-tCYC/2  10
-
ns
CSn
 WRX time
tCSLWL
WRX, WRLX,
WRHX, CSn
EACL:ACE=0
-3tCYC/2  15
ns
EACL:ACE=1
-5tCYC/2  15
WRX
 CSn time
tWHCSH
WRX, WRLX,
WRHX, CSn
-
tCYC/2  15
-
ns
(TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Condition
Value
Unit
Remarks
Min
Max
Valid address
 WRX  time
tAVWL
WRX, WRLX,
WRHX, A[23:16]
EACL:ACE=0
3tCYC/2  20
-
ns
EACL:ACE=1
5tCYC/2  20
-
tADVWL
WRX, WRLX,
WRHX, AD[15:0]
EACL:ACE=0
tCYC  20
-
ns
EACL:ACE=1
2tCYC  20
-



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