MB96F348CWCPMC-GSE2 datasheet(2/109 Pages) CYPRESS

2 / 109 page

MB96340 Series

Document Number: 002-04579 Rev. *A

Page 2 of 109

Features

Feature

Description

Technology

■ 0.18m CMOS

CPU

■ F2MC-16FX CPU

■ Up to 56 MHz internal, 17.8 ns instruction cycle time

■ Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different

addressing modes; barrel shift; variety of pointers)

■ 8-byte instruction execution queue

■ Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available

System clock

■ On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)

■ 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends

on Q-factor).

■ Up to 56 MHz external clock for devices with fast clock input feature

■ 32-100 kHz subsystem quartz clock

■ 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog

■ Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC

oscillator, independently for CPU and 2 clock domains of peripherals.

■ Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode)

■ Clock modulator

On-chip voltage regulator

■ Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power

consumption figures

Low voltage reset

■ Reset is generated when supply voltage is below minimum.

Code Security

■ Protects ROM content from unintended read-out

Memory Patch Function

■ Replaces ROM content

■ Can also be used to implement embedded debug support

DMA

■ Automatic transfer function independent of CPU, can be assigned freely to resources

Interrupts

■ Fast Interrupt processing

■ 8 programmable priority levels

■ Non-Maskable Interrupt (NMI)

Timers

■ Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer,

17-bit Sub clock timer)

■ Watchdog Timer

CAN

■ Supports CAN protocol version 2.0 part A and B

■ ISO16845 certified

■ Bit rates up to 1 Mbit/s

■ 32 message objects

■ Each message object has its own identifier mask

■ Programmable FIFO mode (concatenation of message objects)

■ Maskable interrupt

■ Disabled Automatic Retransmission mode for Time Triggered CAN applications

■ Programmable loop-back mode for self-test operation

USART

■ Full duplex USARTs (SCI/LIN)

■ Wide range of baud rate settings using a dedicated reload timer

■ Special synchronous options for adapting to different synchronous serial protocols

■ LIN functionality working either as master or slave LIN device

MB96F348CWCPMC-GSE2 数据表(PDF) 2 Page - Cypress Semiconductor

MB96F348CWCPMC-GSE2 数据表(HTML) 2 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载