5220-DS02-R datasheet(36/90 Pages) BOARDCOM

36 / 90 page

BCM5220

Preliminary Data Sheet

04/20/04

Broa d c om Co rp o r a t i o n

Page 24

Media Independent Interface (MII) Management Interface: Register Programming

Document

5220-DS04-405-R

MII CONTROL REGISTER

The MII control register bit descriptions are shown in Table 9.

Reset

To reset the BCM5220 by software control, a 1 must be written to bit 15 of the Control register using an MII write operation.

The bit clears itself after the reset process is complete, and need not be cleared using a second MII write. Writes to other

Control register bits have no effect until the reset process is completed, which requires approximately 1 microsecond. Writing

a 0 to this bit has no effect. Since this bit is self-clearing, after a few cycles from a write operation, it returns a 0 when read.

Loopback

The BCM5220 may be placed into loopback mode by writing a 1 to bit 14 of the Control register. Clear the loopback mode

by writing a 0 to bit 14 of the control register, or by resetting the chip. When this bit is read, it returns a 1 when the chip is in

loopback mode, otherwise it returns a 0.

Forced Speed Selection

If auto-negotiation is enabled (both auto-negotiation pin and bit are enabled) or disabled by hardware control (auto-

negotiation pin is pulled-low), this bit has no effect on the speed selection. However, if auto-negotiation is disabled by

software control, the operating speed of the BCM5220 can be forced by writing the appropriate value to bit 13 of the Control

register. Writing a 1 to this bit forces 100BASE-X operation, while writing a 0 forces 10BASE-T operation. When this bit is

read, it returns the value of the software-controlled forced speed selection only. To read the overall state of forced speed

selection, including both hardware and software control, use bit 2 of the Auxiliary Control register (18h).

Table 9: MII Control Register (Address 00000b, 0d, 00h)

Bit

Name

R/W

Description

Default

Soft Reset

R/W

(SC)

1 = PHY reset

0 = Normal operation

Loopback

R/W

1 = Loopback mode

0 = Normal operation

Forced Speed Selection

R/W

1 = 100 Mbps

0 = 10 Mbps

Auto-Negotiation Enable

R/W

1 = Auto-negotiation enable

0 = Auto-negotiation disable

Power Down

0 = Normal operation

Reserveda

R/W

Restart Auto-Negotiation

R/W

(SC)

1 = Restart Auto-negotiation process

0 = Normal operation

Duplex Mode

R/W

1 = Full-duplex

0 = Half-duplex

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

6:0

Reserveda

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = latched low, LH = latched high (LL and LH are cleared

after read operation)

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