5220-DS02-R datasheet(37/90 Pages) BOARDCOM

37 / 90 page

Preliminary Data Sheet

BCM5220

04/20/04

Broa d c om Co rp o r a t i o n

Document

5220-DS04-405-R

Media Independent Interface (MII) Management Interface: Register Programming

Page 25

Auto-Negotiation Enable

Auto-negotiation can be disabled by one of two methods: hardware or software control. If the ANEN input pin is driven to a

logic 0, auto-negotiation is disabled by hardware control. If bit 12 of the Control register is written with a value of 0, auto-

negotiation is disabled by software control. When auto-negotiation is disabled in this manner, writing a 1 to the same bit of

the Control register or resetting the chip re-enables auto-negotiation. Writing to this bit has no effect when auto-negotiation

has been disabled by hardware control. When read, this bit returns the value most recently written to this location, or 1 if it

has not been written since the last chip reset.

Power Down

The power modes of the BCM5220 are not accessible by this MII register bit. Use LOWPWR pin control instead.

Isolate

The PHY can be isolated from its Media Independent Interface by writing a 1 to bit 10 of the Control register. All MII outputs

are tri-stated and all MII inputs are ignored. Because the MII management interface is still active, the isolate mode can be

cleared by writing a 0 to bit 10 of the control register, or by resetting the chip. When this bit is read, it returns a 1 when the

chip is in isolate mode; otherwise it returns a 0.

Restart Auto-Negotiation

Bit 9 of the Control register is a self-clearing bit that allows the auto-negotiation process to be restarted, regardless of the

current status of the auto-negotiation state machine. For this bit to have an effect, auto-negotiation must be enabled. Writing

a 1 to this bit restarts the auto-negotiation, while writing a 0 to this bit has no effect. Because the bit is self-clearing after only

a few cycles, it always returns a 0 when read. The operation of this bit is identical to bit 8 of the Auxiliary Multiple PHY register

(1Eh).

Duplex Mode

By default, the BCM5220 powers up in half-duplex mode. The chip can be forced into full-duplex mode by writing a 1 to bit

8 of the Control register while auto-negotiation is disabled. Half-duplex mode can be resumed by writing a 0 to bit 8 of the

Control register, or by resetting the chip.

Collision Test

Test the COL pin by activating the collision test mode. While in this mode, asserting TXEN causes the COL output to go high

within 512 bit times. Deasserting TXEN causes the COL output to go low within 4 bit times. Writing a 1 to bit 7 of the Control

register enables the collision test mode. Writing a 0 to this bit or resetting the chip disables the collision test mode. When

this bit is read, it returns a 1 when the collision test mode has been enabled; otherwise it returns a 0. This bit should only be

set while in loopback test mode.

Reserved Bits

All reserved MII register bits must be written as 0 at all times. Ignore the BCM5220 output when these bits are read.

5220-DS02-R 数据表(PDF) 37 Page - Broadcom Corporation.

5220-DS02-R 数据表(HTML) 37 Page - Broadcom Corporation.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载