5220-DS02-R datasheet(66/90 Pages) BOARDCOM

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BCM5220

Preliminary Data Sheet

04/20/04

Broa d c om Co rp o r a t i o n

Page 54

Auxiliary Multiple PHY Register

Document

5220-DS04-405-R

AUXILIARY MODE 4 REGISTER (SHADOW REGISTER)

Force LED [1:0]

The SPDLED#, LNKLED#, XMTLED#, RCDLED#, COL_LED#, ACT_LED# and FDX_LED# outputs can be forced to on

state (0) by writing a value of 01 to Force LED [1:0]. These LEDs can be forced to off state (1) by writing a value of 10 to

Force LED {1:0].

Enable Clock During Low Power

If this bit is set to a 1 then the clocks are running in low mode.

Force IDDQ Mode.

If this bit is set to a 1, then the BCM5220 enters IDDQ mode. When the device is in IDDQ mode, everything is disabled. The

BCM5220 requires a hard reset to return to normal mode.

Table 31: Auxiliary Mode 4 Register (Shadow Register 26d, 1Ah)

BIt

Name

R/W

Description

Default

15:6

Reserveda

R/W

Write as 30h, Ignore when read

30h

5:4

Force LED [1:0]

R/W

01 = Force all LED status to on 0 state

10 = Force all LED status to off 1 state

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

R/W

Write as 0, Ignore when read

Enable Clock During Low

Power

R/W

0 = Disables clock during low power modes

1 = Enables clock during low power modes

Force Low Power Mode

R/W

0 = Normal operation

1 = Forces the 5220 to enter the low power mode

Force IDDQ Mode

R/W

0 = Normal operation

1 = Causes theBCM5220 to go to IDDQ mode

Notes: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after

read operation. Use default values of reserved bit(s) when writing to reserved bit(s). MII Shadow register bank 1 is accessed

by setting MII register 1Fh bit 7 to a 1.

5220-DS02-R 数据表(PDF) 66 Page - Broadcom Corporation.

5220-DS02-R 数据表(HTML) 66 Page - Broadcom Corporation.

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