5220-DS02-R datasheet(67/90 Pages) BOARDCOM

67 / 90 page

Preliminary Data Sheet

BCM5220

04/20/04

Broa d c om Co rp o r a t i o n

Document

5220-DS04-405-R

Auxiliary Multiple PHY Register

Page 55

AUXILIARY STATUS 2 REGISTER (SHADOW REGISTER)

MLT3 Detected

The BCM5220 returns a 1 in this bit whenever MLT3 signaling is detected.

APD Enable

When in normal mode, if this bit set to a 1, the BCM5220 enters auto power down mode. If this bit is set, the BCM5220 enters

low power mode whenever the link is lost. When energy is detected the device enters full power mode. Otherwise, it wakes-

up after 2.5s or 5.0s, as determined by the APD Sleep Timer bit. When the BCM5220 wakes up, it sends link pulses and

monitors energy. If the link partner’s energy is detected then the BCM5220 enters full power mode and establishes a link

with the Link partner. If no energy is detected from the link partner, it continues to stay in wake-up mode for a duration

determined by the APD Wake-up Timer before going to low power mode.

APD Sleep TImer

This bit determines how long the BCM5220 stays in low power mode before wake-up. If this bit is a 0, then it waits

approximately 2.5s before wake-up, else 5s.

APD Wake-up TImer [3:0]

This counter determines how long the BCM5220 stays up in wake-up mode before going to low-power mode. This value is

specified in 40-ms increments from 0 to 600 ms. A value of 0 forces the BCM5220 to stay in low-power mode indefinitely. In

this case the BCM5220 requires a hard reset to return to normal mode.

Table 32: Auxiliary Status 2 Register (Shadow Register 27d, 1Bh)

BIt

Name

R/W

Description

Default

MLT3 Detected

R/O

1 = MLT3 Detected

14:6

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

R/O

000h

APD Enable

R/W

0 = Normal mode

1 = Enable auto power down mode

APD Sleep Timer

R/W

0 = 2.5 sec sleep before wake-up

1 = 5.0 sec sleep before wake-up

3:0

APD Wake-up Timer [3:0]

R/W

Duration of wake-up

0001

Notes: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after

read operation. Use default values of reserved bit(s) when writing to reserved bit(s). MII Shadow register bank 1 is accessed

by setting MII register 1Fh bit 7 to a 1.

5220-DS02-R 数据表(PDF) 67 Page - Broadcom Corporation.

5220-DS02-R 数据表(HTML) 67 Page - Broadcom Corporation.

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