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5220-DS02-R 数据表(PDF) 71 Page - Broadcom Corporation. |
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5220-DS02-R 数据表(HTML) 71 Page - Broadcom Corporation. |
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71 / 90 page ![]() Preliminary Data Sheet BCM5220 04/20/04 Broa d c om Co rp o r a t i o n Document 5220-DS04-405-R Auxiliary Status 4 Register (Shadow Register) Page 59 Figure 3: Clock and Reset Timing Table 39 provides the parameters for 100BASE-X transmit timing. Figure 4 illustrates the 100BASE-TX transmit start of packet timing and Figure 5 on page 60 shows the100BASE-TX transmit end of packet timing. Table 39: MII 100BASE-X Transmit Timing Parameter Symbol Min Typ Max Unit TXC Cycle Time 40 ns TXC High/Low Time 16 20 24 ns TXC Rise/Fall Time 2 5 ns TXEN, TXD[3:0] Setup Time to TXC rising TXEN_SETUP 10 ns TXEN, TXD[3:0] Hold Time from TXC rising TXEN_HOLD 0 ns TD ± after TXEN Assert (unsampled) TXEN_TDATA 100 ns TXD to TD ± Steady State Delay TXD_TDATA 100 ns CRS Assert after TXEN Assert TXEN_CRS 11 ns CRS Deassert after TXEN Deassert TXEN_CRS_EOP 11 ns COL Assert after TXEN Assert (while RX) TXEN_COL 17 ns COL Deassert after TXEN Deassert (while RX) TXEN_COL_EOP 17 ns XTALI RESET# Normal PHY RESET_LEN RESET_WAIT CK_HI CK_CYCLE CK_EDGE CK_LO CK_EDGE activity begins here RESET_EDGE RESET_EDGE |
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