5220-DS02-R datasheet(21/90 Pages) BOARDCOM

21 / 90 page

Preliminary Data Sheet

BCM5220

04/20/04

Broa d c om Co rp o r a t i o n

Document

5220-DS04-405-R

MII Management

Page 9

F100

TCK

IPU

Force 100BASE-X Control. When 100BASE-FX mode is not

selected, the F100 function is enabled. When F100 is high and

ANEN is low, the transceiver is forced to 100BASE-TX operation.

When F100 is low and ANEN is low, the transceiver is forced to

10BASE-T operation. When ANEN is high, F100 has no effect on

operation.

Test Clock. This pin becomes TCK if JTAG_EN pin is high.

Clock input used to synchronize JTAG TAP control and data

transfers.

ANEN

TRST#

IPU

Auto-Negotiation Enable. When 100BASE-FX is not selected,

the ANEN function is enabled. ANEN is active high. When pulled

high, auto-negotiation begins immediately after reset. When low,

auto-negotiation is disabled by default.

Test Reset. This pin becomes TRST# if JTAG_EN pin is high.

Asynchronous active low reset input to the JTAG TAP Controller.

Must be set low to ensure the TAP Controller initializes to the

test-logic-reset state.

SD+

SD-

IPD

100BASE-FX Signal Detect. 100BASE-FX mode is selected if

SD+/- pins are presented with a valid PECL differential signal.

Leaving this pin unconnected or connecting them to ground

causes the BCM5220 to operate in TX mode. When 100BASE-

FX is selected, SD+ and SD

− indicate signal quality status on the

fiber optic link. When the signal quality is good, the SD+ pin will

be high relative to the SD

− pin.

TESTEN

IPD

Test Mode Enable. Active high. Can float or be grounded for

normal operation.

LOW_PWR

IPD

Low Power Mode Enable. Active high input places the

BCM5220 into Low Power operation with the chip deactivated

except for the energy detect block and the crystal oscillator.

When asserted with RESET# pulled low, the entire chip is

deactivated (Power Off mode).

ENERGY_DET

O3S

Energy Detection. Active high output indicates the presence of

a signal on RD+/

− receive analog wire pair. Operational in all

modes of operation except IDDQ.

Bias

RDAC

DAC Bias Resistor. Adjusts the current level of the transmit

DAC. A resistor of 1.27 k

Ω±1% must be connected between the

RDAC pin and GND.

LEDs

LNKLED#

TDI

I/OPU

Link Integrity LED. The Link Integrity LED indicates the link

status of the PHY. LNKLED# is driven low when the link to the

PHY is good. When bit 12 of register 1Dh is set to 1, LNKLED#

is driven low when the 100BASE-TX link is good.

Test Data Input. This pin becomes TDI if JTAG_EN is high.

Serial data input to the JTAG TAP controller. This pin is sampled

on the rising edge of TCK.

Table 3: Pin Descriptions (Cont.)

5220KPB 5220KPT

Pin Label

Type

Description

[MSB:LSB]; # = active-low signal, I = input, O = output, I/O = bidirectional, IPU = input w/ internal pull-up, OOD = open-drain

output, O3S = three-state output, B = Bias, PWR = power supply, GND = ground

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