5220-DS02-R datasheet(63/90 Pages) BOARDCOM

63 / 90 page

Preliminary Data Sheet

BCM5220

04/20/04

Broa d c om Co rp o r a t i o n

Document

5220-DS04-405-R

Auxiliary Multiple PHY Register

Page 51

Block TXEN Mode

When this mode is enabled, short IPGs of 1, 2, 3 or 4 TXC cycles results in the insertion of two IDLEs before the beginning

of the next packet’s JK symbols.

AUXILIARY MULTIPLE PHY REGISTER

HCD Bits

Bits 15:11 of the Auxiliary Multiple PHY register are 5 read-only bits that report the Highest Common Denominator (HCD)

result of the auto-negotiation process. Immediately upon entering the link pass state after each reset or restart auto-

negotiation, only 1 of these 5 bits is 1. The link pass state is identified by a 1 in bit 6 or 7 of this register. The HCD bits are

reset to 0 every time auto-negotiation is restarted or the BCM5220 is reset. For their intended application, these bits uniquely

identify the HCD only after the first link pass after reset or restart of auto-negotiation. On later Link Fault and subsequent re-

negotiations, if the ability of the link partner is different, more than 1 of the above bits can be active.

Table 29: Auxiliary Multiple PHY Register (Address 30d, 1Eh)

Bit

Name

R/W

Description

Default

HCD_TX_FDX

1 = Auto-negotiation result is 100BASE-TX full-duplex

HCD_T4

1 = Auto-negotiation result is 100BASE-T4

HCD_TX

1 = Auto-negotiation result is 100BASE-TX

HCD_10BASE-T_FDX

1 = Auto-negotiation result is 10BASE-T full-duplex

HCD_10BASE-T

1 = Auto-negotiation result is 10BASE-T

10:9

Reserveda

Ignore when read

Restart Auto-Negotiation

R/W

(SC)

1 = Restart auto-negotiation process

0 = (No effect)

Auto-Negotiation Complete

1 = Auto-negotiation process completed

0 = Auto-negotiation process not completed

Acknowledge Complete

1 = Auto-negotiation acknowledge completed

Acknowledge Detected

1 = Auto-negotiation acknowledge detected

Ability Detect

1 = Auto-negotiation waiting for LP ability

Super Isolate

R/W

1 = Super isolate mode

0 = Normal operation

Reserveda

Ignore when read

10BASE-T Serial Mode

R/W

1 = Enable 10BASE-T serial mode

0 = Disable 10BASE-T serial mode

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

R/W

Write as 0, Ignore when read

Notes: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after

read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

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