5220-DS02-R datasheet(55/90 Pages) BOARDCOM

55 / 90 page

Preliminary Data Sheet

BCM5220

04/20/04

Broa d c om Co rp o r a t i o n

Document

5220-DS04-405-R

Auxiliary Control/Status Register

Page 43

AUXILIARY CONTROL/STATUS REGISTER

The Auxiliary Control/Status register bit descriptions are shown in Table 23.

Jabber Disable

10BASE-T operation only. Bit 15 of the Auxiliary Control register allows the user to disable the jabber detect function, defined

in the IEEE standard. This function shuts off the transmitter when a transmission request has exceeded a maximum time

limit. By writing a 1 to bit 15 of the Auxiliary Control register, the jabber detect function is disabled. Writing a 0 to this bit or

resetting the chip restores normal operation. Reading this bit returns the value of jabber detect disable.

Link Force

Writing a 1 to bit 14 of the Auxiliary Control register allows the user to disable the Link Integrity state machines, and place

the BCM5220 into forced link pass status. Writing a 0 to this bit or resetting the chip restores the Link Integrity functions.

Reading this bit returns the value of the force link bit.

HSQ and LSQ

Extend or decrease the squelch levels for detection of incoming 10BASE-T data packets. The default squelch levels

implemented are those defined in the IEEE standard. The high-and low-squelch levels are useful for situations where the

IEEE-prescribed levels are inadequate. The squelch levels are used by the CRS/LINK block to filter out noise and recognize

only valid packet preambles and link integrity pulses. Extending the squelch levels allows the BCM5220 to operate properly

Table 23: Auxiliary Control/Status Register (Address 24d, 18h)

Bit

Name

R/W

Description

Default

Jabber Disable

R/W

1 = Jabber function disabled

0 = Jabber function enabled

Force Link

R/W

1 = Force 10BASE-T link pass

0 = Normal 10BASE-T link operation

13:8

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

Ignore when read

000000

7:6

HSQ : LSQ

R/W

These two bits define the squelch mode of the

10BASE-T Carrier Sense mechanism

00 = Normal Squelch

01 = Low Squelch

10 = High Squelch

11 = Not Allowed

5:4

Edge Rate [1:0]

R/W

00 = 1 ns

01 = 2 ns

10 = 3 ns

11 = 4 ns

Auto-Negotiation Indication

1 = Auto-negotiation activated

0 = Speed forced manually

ANEN Pin

Force 100/10 Indication

1 = Speed forced to 100BASE-X

0 = Speed forced to 10BASE-T

F100 Pin

Speed Indication

1 = 100BASE-X

0 = 10BASE-T

Full-Duplex Indication

1 = Full-duplex active

0 = Full-duplex not active

FDX Pin

5220-DS02-R 数据表(PDF) 55 Page - Broadcom Corporation.

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