5220-DS02-R datasheet(59/90 Pages) BOARDCOM

59 / 90 page

Preliminary Data Sheet

BCM5220

04/20/04

Broa d c om Co rp o r a t i o n

Document

5220-DS04-405-R

Auxiliary Mode 2 Register

Page 47

Interrupt Mask

Master Interrupt Mask. When this bit is set, no interrupts will be generated, regardless of the state of the other MASK bits.

FDX Change

A 1 indicates a change of Duplex status since last register read. Register read clears the bit.

SPD Change

A 1 indicates a change of Speed status since last register read. Register read clears the bit.

Link Change

A 1 indicates a change of Link status since last register read. Register read clears the bit.

Interrupt Status

Represents status of the INTR# pin. A 1 indicates that the interrupt mask is off and that one or more of the change bits are

set. Register read clears the bit.

AUXILIARY MODE 2 REGISTER

10BASE-T Dribble Bit Correct

When enabled, the PHY rounds down to the nearest nibble when dribble bits are present on the 10BASE-T input stream.

Table 26: Auxiliary Mode 2 Register (Address 27d, 1Bh)

BIt

Name

R/W

Description

Default

15:12

Reserveda

Ignore when read

10BASE-T Dribble Bit Correct

R/W

1 = Enable, 0 = Disable

Token Ring Mode

R/W

1 = Enable, 0 = Disable

HSTR FIFO Enable

R/W

1 = Enable, 0 = Disable

Reserveda

Ignore when read

Block 10BT Echo Mode

R/W

1 = Enable, 0 = Disable

Traffic Meter LED Mode

R/W

1 = Enable, 0 = Disable

Activity LED Force On

R/W

1 = ON, 0 = Normal operation

Reserveda

R/W

Ignore when read

Reserveda

R/W

Write as 1, Ignore when read

Activity/Link LED Mode

R/W

1 = Enable, 0 = Disable

Qual Parallel Detect Mode

R/W

1 = Enable, 0 = Disable

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

Ignore when read

Notes: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after

read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

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