5220-DS02-R datasheet(20/90 Pages) BOARDCOM

20 / 90 page

BCM5220

Preliminary Data Sheet

04/20/04

Broa d c om Co rp o r a t i o n

Page 8

MII Management

Document

5220-DS04-405-R

RXDV

O3S

MII Receive Data Valid. Active high. Indicates that a receive

frame is in progress, and that the data stream present on the

RXD output pins is valid.

RXER

O3S

MII Receive Error Detected. Active high. Indicates that an error

is occurring during a receive frame.

CRS/

CRS_DV

O3S

MII Carrier Sense. Active high. Indicates traffic on link. In

100BASE-X modes, CRS is asserted when a non-idle condition

is detected in the receive data stream and deasserted when idle

or a valid end of stream delimiter is detected. In 10BASE-T

mode, CRS is asserted when a valid preamble is detected and

deasserted when end-of-file or an idle condition is detected. CRS

is also asserted during transmission of packets except in full-

duplex modes. CRS is an asynchronous output signal.

COL

O3S

Collision Detect. In half-duplex modes, active high output

indicates that a collision has occurred. In full-duplex mode, COL

remains low. COL is an asynchronous output signal.

MDIO

I/OPU

Management Data I/O. This serial input/output bit is used to read

from and write to the MII registers. The data value on the MDIO

pin is valid and latched on the rising edge of MDC.

MDC

IPD

Management Data Clock. The MDC clock input must be

provided to allow MII management functions. Clock frequencies

up to 12.5 MHz are supported.

Mode

RESET#

IPU

Reset. Active Low. Resets the BCM5220. Also used to enable

Power Off and Low Power modes.

PHYAD4

PHYAD3/PAUSE

PHYAD2/

ACT_LED#

PHYAD1/

COL_LED#

PHYAD0/

FDX_LED#

I/OPD

PHY Address Selects PHYAD[4:0]. These inputs set the MII

management PHY address. These pins are sampled only during

power-on reset. During normal operation these pins become

outputs.

PAUSE. Status of the link partner’s PAUSE bit, bit 10d of MII Link

Partner Ability register 05d.

Activity LED. Active low. The activity LED is driven low for

approximately 80 ms each time there is receive or transmit

activity while in the link pass state.

Collision Detect LED. Active low. This is a stretched COL signal

(pin 61) that is suitable for LED display.

Full-Duplex LED. The Full-Duplex LED is driven low when

operating in full-duplex mode and driven high in half-duplex

mode.

FDX

IPD

Full-Duplex Mode. When auto-negotiation is disabled, the FDX

pin is logically ORed with register 00, bit 8 to select full-duplex (1)

or half-duplex (0) operation.

Table 3: Pin Descriptions (Cont.)

5220KPB 5220KPT

Pin Label

Type

Description

[MSB:LSB]; # = active-low signal, I = input, O = output, I/O = bidirectional, IPU = input w/ internal pull-up, OOD = open-drain

output, O3S = three-state output, B = Bias, PWR = power supply, GND = ground

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