ADM1266ACPZ-R7 datasheet(28/62 Pages) AD

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ADM1266

Data Sheet

Rev. A | Page 28 of 62

APPLICATIONS INFORMATION

OVERVIEW

The ADM1266 Super Sequencer is capable of sequencing,

margining, trimming, supervising output voltage for OV and

UV conditions, providing fault management, and voltage read-

back for 16 dc-to-dc converters. Multiple ADM1266 devices can

be synchronized to operate in unison using the ID_SCL and

ID_SDA pins. The ADM1266 uses a PMBus-compliant interface

and command set.

POWERING THE ADM1266

The ADM1266 can be powered by applying a voltage from 3 V

to 15 V on the VH1 or VH2 pin. Internal linear regulators convert

this voltage down to 3.3 V, which drives all of the internal circuitry

in each device. It is not recommended to connect both VH1 and

VH2 to the same voltage levels because the ripple on the two

voltages may cause the arbitrator circuit to constantly toggle. In

a system with multiple ADM1266 devices, it is important that all

the devices are powered from the same voltage rail.

PCB ASSEMBLY AND LAYOUT SUGGESTIONS

The ADM1266 requires capacitors (see the Capacitors section).

To be effective, these capacitors must be high quality, ceramic

dielectric capacitors, such as X5R or X7R, and must be placed as

close to the chip as possible. The PCB layout must adhere to

layout guidelines. A multilayer PCB that dedicates a layer to

power and ground is recommended. Low resistance and low

inductance power and ground connections are important to

minimize power supply noise and ensure proper device

operation.

CAPACITORS

Place a 10 µF bypass capacitor and a 0.1 µF decoupling

capacitor on both the VH1 and VH2 pins.

Place a 68 µF capacitor and a 0.1 µF capacitor on the

AVDD_CAP pin.

Place a 10 µF capacitor and a 0.1 µF capacitor on the

DVDD_CAP pin

Place a 2.2 µF capacitor and a 0.1 µF capacitor between the

REFOUT and REFGND pins.

GROUND CONNECTIONS

Connect the exposed pad to the GND pin. Star connect the

GND pin to the REFGND pin.

PMBUS/I2C

Each ADM1266 must be configured for a unique address. The

address can be set by connecting a resistor between the ADDR pin

and the GND pin. See Table 10 for the corresponding address

values. Check addresses for collision with other devices on the

bus and any global addresses.

The pull-up resistors on the PMBus pins must not be connected

to AVDD_CAP. If another device on the PMBus line provides a

strong pull-down on AVDD_CAP, the ADM1266 shuts down or

enters UVLO.

IDB

For a board with multiple ADM1266 devices that are part of the

same system, connect the ID_SCL and ID_SDA pin, using an

external pull-up resistor of 2.2 kΩ that is connected to the

AVDD_CAP pin of any ADM1266.

VOLTAGE SENSING

If an external resistor divider is used, calculate the size of the

resistors so that 0.7 V shows up on the VPx pins of the ADM1266.

When sensing directly, use a 100 Ω resistor in series to avoid

any latch-ups on the pins. The VH1 and VH2 pins do not

require this series resistance.

PDIOs AND GPIOs

The PDIOs have a weak, 20 kΩ, internal pull-down resistor.

Therefore, the PDIOs do not require the external pull-down

resistors during power-up.

Verify that the voltage and current ratings are not exceeded.

DAC OUTPUTS

Select an appropriate resistor for the desired margin range on a

DAC output. Refer to the Power Studio GUI for assistance.

CLOCK

To use the accurate time stamping and clocking function, use

an external oscillator and capacitors between the XTAL1 and

XTAL2 pins. If this function is not used, an external clock

source is not required.

On a board with multiple ADM1266 devices, only one external

oscillator is required. Connect the SYNC pins of all the

ADM1266 devices.

UNUSED PINS

Connect all unused pins to GND.

ADM1266ACPZ-R7 数据表(PDF) 28 Page - Analog Devices

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