ADM1266ACPZ-R7 datasheet(16/62 Pages) AD

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ADM1266

Data Sheet

Rev. A | Page 16 of 62

Threshold Settings

The UV and OV thresholds are set using the commands in Table 7.

Table 7. UV and OV Threshold Commands

Command

Description

VOUT_MODE

0x20

Used for setting the

exponent for linear

PMBus calculations for

the following commands

VOUT_OV_WARN_LIMIT,

VOUT_UV_WARN_LIMIT

0x42,

0x43

Used for setting mantissa

for linear PMBus

calculation of warning

limits

VOUT_OV_FAULT_LIMIT,

VOUT_UV_FAULT_LIMIT

0x40,

0x44

Used for setting mantissa

for linear PMBus

calculation of fault limits

VOUT_OV_HYST_LIMIT,

VOUT_UV_HYST_LIMIT

0xD0,

0xD1

Used for setting mantissa

for linear PMBus

calculation of hysteresis

limits

Voltage Readback and Status

The ADM1266 has an on-board, 12-bit accurate ADC for

voltage readback over the PMBus using the READ_VOUT

command (Register 0x8B). Inputs to the ADC consist of the

17 SFD inputs (VHx and VPx pins). The inputs to the ADC

come from the back of the input attenuators on the VPx and

VHx pins, as shown in Figure 9.

Supplies can also be connected to the input pins purely for ADC

readback, even though these pins may go above the expected

supervisory range limits (but not above the absolute maximum

ratings on these pins). For example, a 1.5 V supply connected to

the VP1 pin on the lowest range (0.4 V to 1.0 V) can be correctly

read out as on the ADC, but it always sits above any supervisory

limits that can be set on that pin.

Voltage Trimming

Use the VOUT_TRIM PMBus command (Register 0x22) to add

an additional offset trim to all the threshold settings and for voltage

readback. This command can be used to remove any inaccuracies

generated by the external components.

PROGRAMMABLE DRIVER INPUT/OUTPUTS

Supply Sequencing Through Configurable Output

Drivers

The programmable driver input/output (PDIOx) pins are typically

used to drive logic enables on external supplies or as digital

inputs into the sequencing engine. The sequence in which the

PDIOx pins are asserted (and, therefore, the supplies are turned

on) is controlled by the SE firmware. The SE determines the action

that is taken with the PDIOx pins, based on the condition of the

ADM1266 inputs. Therefore, the PDIOx pins can be set up to

assert when the SFDs are in tolerance and no faults are received

from any of the inputs of the device.

The PDIOx pins can also be used to provide a power-good signal,

when all the SFDs are in tolerance, or a reset output if one of the

SFDs goes out of specification (this power-good signal can be

used as a status signal for a DSP, FPGA, or other microcontroller).

The open-drain nature of the PDIOx pins also allows them to

be used to drive status LEDs.

The output stage of the PDIOx pins has programmable pull-up

and pull-down options. The PDIOx pins can be programmed as

follows:

•

Push/pull to AVDD_CAP. When using a PDIOx pin in a

push/pull configuration, a 20 kΩ resistor in series is recom-

mended to limit the current drawn from the PDIOx pin.

•

Open drain with an internal 20 kΩ pull-up resistor to

AVDD_CAP.

•

Open drain with an external pull-up resistor up to 20 V.

•

Open source with an internal 20 kΩ pull-down resistor to

GND.

•

Open source with external pull-down resistor to GND.

•

High-Z.

•

Internal 20 kΩ pull-up resistor to AVDD_CAP.

•

Internal 20 kΩ pull-down resistor to GND.

Ω 20kΩ

20k

Ω

AVDD_CAP (3.3V)

PDIOx

INPUT

OUTPUT

CONFIG

12V

Figure 10. Programmable Driver Input/Output

Default Output Configuration

All of the internal registers in an unprogrammed ADM1266

device from the factory are set to 0. Because of this default setting,

the PDIOx pins are pulled to GND by a weak (20 kΩ), on-chip,

pull-down resistor.

As the input supply to the ADM1266 ramps up on VHx, all

PDIOx pins behave as follows:

•

Input supply = 0 V to 1.5 V. The PDIOx pins are high

impedance.

•

Input supply = 1.5 V to 2.7 V. The PDIOx pins are pulled to

GND by a weak (20 kΩ), on-chip, pull-down resistor.

•

Supply > 2.7 V. Factory programmed devices continue to

pull all PDIOx pins to GND by a weak (20 kΩ), on-chip,

pull-down resistor. Programmed devices download current

EEPROM configuration data, and the programmed setup is

latched. The PDIOx pin then goes to the state demanded by

the configuration. This configuration provides a known

condition for the PDIOx pins during power-up. If the pin is

configured to output, after downloading the configuration

and before the sequence is run, the ADM1266 senses the

voltage on the pin and drives the pin to the same level as the

voltage sensed on the pin.

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