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ADM1266ACPZ-R7 数据表(PDF) 12 Page - Analog Devices

部件名 ADM1266ACPZ-R7
功能描述  Cascadable Super Sequencer Margin Control and Fault Recording
PDF  62 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADM1266ACPZ-R7 数据表(HTML) 12 Page - Analog Devices

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ADM1266
Data Sheet
Rev. A | Page 12 of 62
Pin No.
Mnemonic1
Description
43
SYNC
32.768 kHz Clock Timing Synchronization Input/Output. This pin can be used to provide a
clock signal to other ADM1266 devices on the board, or a 32.768 kHz input signal can be
provided to the ADM1266 from an external clock source. The default start-up condition of this
pin is high impedance.
46
SDA
PMBus Data. SDA is a bidirectional, open-drain pin that requires an external pull-up resistance
of 2.2 kΩ.
47
SCL
PMBus Clock. SCL is bidirectional, open-drain pin that requires an external pull-up resistance
of 2.2 kΩ.
EPAD
Exposed Pad. The exposed pad must be soldered to the ground plane.
1 Connect all unused pins to GND.



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