ADM1266ACPZ-R7 datasheet(32/62 Pages) AD

32 / 62 page

ADM1266

Data Sheet

Rev. A | Page 32 of 62

PMBus ADDRESS SELECTION

Control of the ADM1266 is implemented via the I2C interface.

The ADM1266 device is connected to the I2C bus as a slave

device under the control of a master device. The PMBus address

of the ADM1266 is set by connecting an external resistor from

the ADDR pin to GND. Table 10 lists the recommended resistor

values and associated PMBus addresses.

Table 10. PMBus Address Settings

PMBus Address

1% Resistor (kΩ) (E96 Series)

0x40

0.422

0x41

1.5

0x42

2.67

0x43

4.12

0x44

5.36

0x45

7.15

0x46

8.87

0x47

10.7

0x48

12.7

0x49

14.7

0x4A

16.9

0x4B

19.1

0x4C

21.5

0x4D

24.3

0x4E

27.4

0x4F

31.6

FAST MODE

Fast mode (400 kHz) uses essentially the same mechanics as

the standard mode of operation. The PMBus slave is capable of

communicating with a master device operating in standard

mode (100 kHz) or fast mode.

10-BIT ADDRESSING

The PMBus slave device does not support 10-bit addressing as

defined in the I2C specification.

PACKET ERROR CHECKING

The PMBus controller implements PEC to improve reliability

and communication robustness. Packet error checking is

implemented by appending a PEC byte at the end of the

message transfer. The PEC byte is calculated using a CRC-8

algorithm on all address, command, and data bytes from the

start to stop bits (excluding the acknowledge, no acknowledge,

start, restart, and stop bits). The PEC byte is appended to the

end of the message by the device that supplied the last data byte.

The receiver of the PEC byte is responsible for calculating its

internal PEC code and comparing it to the received PEC byte.

The ADM1266 can communicate with master PMBus devices

that support PEC, as well as with master devices that do not

support PEC. If a PEC byte is available, the PMBus device

checks the PEC byte and issues an acknowledge if the PEC byte

is correct. If the PEC byte comparison fails, the PMBus device

issues a no acknowledge in response to the PEC byte and does

not process the command sent from the master.

The PMBus device uses built in hardware to calculate the PEC

code using the CRC-8 polynomial, C(x) = x8 + x2 + x1 + 1. The

PEC code is calculated one byte at a time, in the order that the

bytes are received. In a read transaction, the PMBus device

appends the PEC byte following the last data byte. In a write

transaction, the PMBus device compares the received PEC byte

to the internally calculated PEC code.

ELECTRICAL SPECIFICATIONS

All logic complies with the electrical specification outlined in

the PMBus Power System Management Protocol Specification

Part 1 (Revision 1.2, September 6, 2010).

ADM1266ACPZ-R7 数据表(PDF) 32 Page - Analog Devices

ADM1266ACPZ-R7 数据表(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载