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ADM1266ACPZ-R7 数据表(PDF) 20 Page - Analog Devices

部件名 ADM1266ACPZ-R7
功能描述  Cascadable Super Sequencer Margin Control and Fault Recording
PDF  62 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADM1266ACPZ-R7 数据表(HTML) 20 Page - Analog Devices

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ADM1266
Data Sheet
Rev. A | Page 20 of 62
SUPPLY MARGINING
OVERVIEW
Due to tolerances of circuit components, input voltage ranges,
and variations in reference voltages, load, and temperature, for
example, the output voltage of the dc-to-dc converter deviates
from the nominal setpoint value. The worst case conditions
need to be simulated on the power supply during manufacturing
and production, and the corner conditions can be measured to
check for an out-of-limit condition. Additionally, the accuracy
of the output voltage is also a critical factor for some applications
and must be tightly maintained when the tolerance of the output
voltage resistive divider is large (see Figure 12).
The procedure of ensuring this output voltage regulation is
called margining (or voltage margining). This voltage margining is
accomplished by the use of an on-chip DAC that pulls up/down
the feedback node of the error amplifier of the power controller.
A typical application circuit for margining is shown in Figure 12.
Using nodal analysis and basic circuit theory, modifying the
feedback node changes the output voltage and, typically, there is
an inversely proportional relationship between the output of the
DAC and the output voltage.
Because the ADM1266 has nine internal DACs, margining is
possible on nine rails.
OUTPUT
DC-TO-DC
CONVERTER
FEEDBACK
GND
R1
R2
ATTENUATION
RESISTOR
R3
VHx/VPx
ADM1266
DACx
MUX
ADC
DAC
CONTROL
BLOCK
R4
R5
Figure 12. Typical Application Circuit for Margining
Margining can be performed two ways: open-loop margining
and closed-loop margining.
The margining is actuated by a DAC and a series resistor that are
connected to the feedback node of the power supply controller
(see Figure 12). The equivalent change in output voltage can be
determined by the following equations:
R1
V
V
R2
V
R3
V
V
FB
OUT
FB
FB
DAC
=
+
(1)
R2
R1
R2
V
V
OUT
FB
+
×
=
(2)
Subtracting the two equations yields
(
)
DAC
FB
OUT
V
V
R3
R1
V
=
Table 8. DAC_CODE_CONFIGURATION[3:1], Register 0xEB,
DAC Ranges
Bits[3:1]
Midcode
Voltage (V)
Minimum
Voltage
Output (V)
Maximum
Voltage
Output (V)
0x00= 3’b000
0.506
0.202
0.808
0x01= 3’b001
0.607
0.303
0.909
0x02= 3’b010
0.809
0.505
1.111
0x03= 3’b011
1.011
0.707
1.313
0x04= 3’b100
1.263
0.959
1.565
Open-Loop Margining
In open-loop margining, the user has direct access to the
internal DACs. The DAC forces a voltage on the feedback node
of the power controller, which causes a deviation in the output
voltage. Typical values for this test are ±1%, ±2.5%, ±5%, ±7.5%,
and ±10% of the nominal output voltage. The user can program
up to 16 preset values, and can use a pointer command to instruct
the device regarding the value that must be loaded into the DAC.
Both the preset values and the value of the pointer can be saved
into the memory. At power-up, the device downloads the
settings and configures the DAC automatically.
Closed-Loop Margining
Closed-loop margining is the preferred method of margining. It
determines the ability of the power supply to regulate the output
under extreme corner conditions. It is recommended to use the
Power Studio software because it provides all related calculations
for resistors and parameters for this feature.
The ADM1266 uses the PMBus Power System Management
Protocol Specification (Revision 1.2, September 6, 2010)
command set that offers the margining commands through the
following commands:
OPERATION (Register 0x01)
VOUT_MARGIN_HIGH (Register 0x25)
VOUT_MARGIN_LOW (Register 0x26)
VOUT_SCALE_LOOP (Register 0x29)
VOUT_COMMAND (Register 0x21)
VOUT_MARGIN_LOOP (Register 0xDA)
MARGIN_CONFIGURATION (Register 0xDB)
These commands enable margining, position the output voltage
at either the high or low value, monitor the feedback node, and
set the ratio of R1 and R3.



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