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ADM1266ACPZ-R7 数据表(PDF) 1 Page - Analog Devices

部件名 ADM1266ACPZ-R7
功能描述  Cascadable Super Sequencer Margin Control and Fault Recording
PDF  62 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADM1266ACPZ-R7 数据表(HTML) 1 Page - Analog Devices

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Cascadable Super Sequencer with Margin
Control and Fault Recording
Data Sheet
ADM1266
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Complete supervisory and sequencing solution for up to
17 supplies
Expandable to 257 supplies with additional ADM1266 ICs
connected to the 2-wire interdevice bus
Fully programmable sequencing engine
17 supply fault detectors enable real time supervision of
supplies
0.4 V to 15 V on VH1 to VH4 (VHx)
0.4 V to 5 V on VP1 to VP13 (VPx)
Device powered by the higher of VH1 and VH2 inputs for
improved operating redundancy
12-bit ADC for readback of all supervised voltages
Black box nonvolatile fault recording
16 PDIOs
9 GPIOs
9 voltage output 8-bit DACs allow voltage margining
adjustment via dc-to-dc converter trim/feedback node
Main and backup memory
Industry standard PMBus interface compliant
Available in a 9 mm × 9 mm, 64-lead package
APPLICATIONS
Communications infrastructure
Industrial test and measurement
GENERAL DESCRIPTION
The ADM1266 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in systems with up to 17 supplies.
For systems with more supplies (up to 257), the operation of up
to 16 ADM1266 devices can be synchronized through a proprie-
tary 2-wire interface (interdevice bus).
The sequencing engine (SE) monitors the supply fault detectors
(SFDs), programmable driver input/outputs (PDIOs), general-
purpose inputs/outputs (GPIOs), and timers, and controls the
PDIOs and GPIOs to sequence the supplies up and down as
required. The logical core of the device is an ARM® Cortex-M3
microcontroller. The firmware is supplied by Analog Devices,
Inc., and all configuration is performed through an intuitive
graphic user interface (GUI).
Additionally, the ADM1266 integrates an analog-to-digital
converter (ADC) and voltage output digital-to-analog converters
(DACs) that can be used to adjust either the feedback node or
reference of a dc-to-dc converter to implement a closed-loop,
autonomous, margining system.
A block of nonvolatile EEPROM is available to record voltage,
time, and fault information when instructed to by the sequencing
engine configuration.
FUNCTIONAL BLOCK DIAGRAM
+
+
GLITCH
FILTER
OV
DAC
UV
DAC
GLITCH
FILTER
VH1
PDIO1
PDIO16
VH4
VP1
VP13
PMBus
INTERFACE
INTERDEVICE
BUS
DAC
CONTROL
SCL
SDA
12-BIT
SAR ADC
PROGRAMMABLE
SEQUENCING
ENGINE
LOGIC BLOCK
MARGINING
EEPROM AND SRAM
PROGRAMMABLE
DRIVE
OUTPUTS/INPUTS
GPIOs
DAC
DAC
GPIO1
GPIO9
ID_SDA
ID_SCL
DAC1
DAC9
Figure 1.


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