ADM1266ACPZ-R7 datasheet(24/62 Pages) AD

24 / 62 page

ADM1266

Data Sheet

Rev. A | Page 24 of 62

SYSTEM LOGIC BLOCK

The ADM1266 features a user configurable combinational logic

block. The input to the logic block can be the status of VHx, VPx, a

GPIO, or PDIO, and the output sets the PDIOs or GPIOs.

The logic block operates independent of the SE and margining

block. The logic block has lower priority than the SE. As a

result, if the sequencing engine is busy running a sequence, the

output of the logic blocks is delayed until completion of the

present task.

The logic function consists of five core logic elements: AND,

OR, NAND, NOR, and NOT. Multiple logic elements can be

cascaded to achieve any user defined logic combination.

The inputs to the logic gates can be a combination of PDIOs,

GPIOs, VHx/VPx warnings, VHx/VPx faults, and the output of

other logic gates.

The output of the logic gates can be used to drive the GPIOs,

PDIOs, or the input of other logic gates.

In a multiple device system, the inputs and outputs from multiple

devices cannot be used in the same logic block because the logic

function block does not use the IDB. The output of logic function

from one ADM1266 device can be propagated to another by

using a GPIO or PDIO.

The maximum number of inputs to a logic element or a

cascaded logic element is 256.

The logic is configured using the manufacture specific command,

LOGIC_CONFIGURATION (Register 0xE0). It is recommend

to use the Power Studio software for programming the logic

blocks to the specifications of the user.

For example, in a system with three voltage rails, UV or OV

warning status of each rail can be logically OR’ed together to

set a single status signal.

ADM1266ACPZ-R7 数据表(PDF) 24 Page - Analog Devices