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ADM1266ACPZ-R7 数据表(PDF) 11 Page - Analog Devices |
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ADM1266ACPZ-R7 数据表(HTML) 11 Page - Analog Devices |
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11 / 62 page  Data Sheet ADM1266 Rev. A | Page 11 of 62 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GPIO1 GPIO2 GPIO3 DVDD_CAP GPIO4 ID_SCL SDA ID_SDA GPIO7 GPIO6 GPIO5 SYNC GPIO8 GPIO9 SCL PDIO16 VP7 VP6 VP5 REFOUT REFGND DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8 DAC9 XTAL2 XTAL1 ADM1266 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE. Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic1 Description 1 to 3, 24 to 27, 59 to 64 VP1 to VP13 Low Voltage Inputs to Supply Fault Detectors. These pins monitor voltages of up to 5 V. 4 REFOUT Reference Output. A capacitor must be connected between this pin and REFGND. A 2.2 µF capacitor is recommended for this purpose. 5 REFGND Ground Return for On-Chip Reference Circuits. Star connect this ground to the GND pin. 6 to 14 DAC1 to DAC9 Voltage Output DACs. These DACs can be used for margining and trimming the supply rails. 15 XTAL2 Crystal Input 2. This pin is configured as the 32.768 kHz crystal input. It can also be configured as high impedance. 16 XTAL1 Crystal Input 1. This pin is configured as the 32.768 kHz crystal input. It can also be configured as high impedance. 17 ADDR PMBus Address Select Resistor. A resistor to GND sets one of 16 addresses. 18 to 21 VH1 to VH4 High Voltage Input to Supply Fault Detectors. These pins can monitor voltages of up to 15 V. The highest voltage from VH1 to VH2 powers the ADM1266 via the supply arbitrator. 22 GND Supply Ground. 23 AVDD_CAP Analog Supply Voltage. Linearly regulated from the higher voltage of the VH1 and VH2 pins to 3.3 V (typical). Note that a capacitor must be connected between this pin and GND. A 68 µF or larger capacitor is recommended for this purpose 28 to 32, 48 to 58 PDIO1 to PDIO16 Programmable Driver Inputs/Outputs. These pins default to a 20 kΩ pull-down resistor at power-up. 33 to 35, 37 to 40, 44, 45 GPIO1 to GPIO9 General-Purpose Inputs/Outputs. The default start-up condition of these pins is high impedance. 36 DVDD_CAP Digital Supply Voltage (1.8 V Typical). Note that a capacitor must be connected between this pin and GND. A 2.2 µF capacitor (or larger), type X5R/10 V (or better), size 0402 (or larger) is recommended for this purpose. 41 ID_SDA Interdevice Communications Bus Data Signal. ID_SDA is a bidirectional, open-drain pin that requires an external pull-up resistor of 2.2 kΩ. It is recommended that the pull-up source be AVDD_CAP. The default start-up condition of this pin is high impedance. 42 ID_SCL Interdevice Communications Bus Clock Signal. ID_SCL is a bidirectional, open-drain pin that requires an external pull-up resistor of 2.2 kΩ. It is recommended that the pull-up source be AVDD_CAP. The default start-up condition of this pin is high impedance. |
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