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ADM1266ACPZ-R7 数据表(PDF) 8 Page - Analog Devices

部件名 ADM1266ACPZ-R7
功能描述  Cascadable Super Sequencer Margin Control and Fault Recording
PDF  62 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADM1266ACPZ-R7 数据表(HTML) 8 Page - Analog Devices

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ADM1266
Data Sheet
Rev. A | Page 8 of 62
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
BUFFERED VOLTAGE OUTPUT DACs
Resolution
8
Bits
Code 0x7F Output Voltage
0.2 V to 0.8 V
0.501
0.506
0.516
V
0.3 V to 0.9 V
0.603
0.607
0.618
V
0.5 V to 1.1 V
0.804
0.809
0.820
V
0.7 V to 1.3 V
1.005
1.011
1.021
V
0.95 V to 1.55 V
1.256
1.264
1.273
V
Output Voltage Range
606
mV
Same range, independent of center point
LSB Step Size
2.376
mV
DAC Supply Currents
3
mA
Maximum total source for all DAC pins
DAC Leakage Current
1
µA
Maximum Load Current
Source
0.25
mA
Sink
0.25
mA
Maximum Load Capacitance
50
pF
Settling Time to 50 pF Load
2
µs
ADC
Signal Range
0
VREF
V
Resolution
12
Bits
Round Robin Time
5
ms
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
2.1
V
Input Low Voltage, VIL
0.8
V
Output Low Voltage, VOL
0.4
V
Clock Frequency, fSCLK
400
kHz
Bus Free Time, tBUF
1.3
µs
Start Setup Time, tSU;STA
0.6
µs
Stop Setup Time, tSU;STO
0.6
µs
Start Hold Time, tHD;STA
0.6
µs
SCL Low Time, tLOW
1.3
µs
SCL Low Timeout, tLOW:MAX
35
ms
PMBus resets if this value is exceeded
SCL High Time, tHIGH
0.6
50
µs
SCL, SDA Rise Time, tR
300
ns
SCL, SDA Fall Time, tF
300
ns
Data Setup Time, tSU;DAT
100
ns
Data Hold Time, tHD;DAT
300
ns
ADDR PIN PULL-UP CURRENT
45
50
55
µA
SYNC
Input High Voltage, VIH
2.1
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
2.6
AVDD_CAP
V
Output Low Voltage, VOL
0.5
V
Clock Frequency, fSCLK
32.768
kHz
INTERDEVICES BUS (IDB)
Input High Voltage, VIH
2.1
V
Input Low Voltage, VIL
0.8
V
Output Low Voltage, VOL
0.4
V
Clock Frequency, fSCLK
1
MHz



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