| 数据搜索系统,热门电子元器件搜索 |
|
WM8802SCFV 数据表(PDF) 34 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8802SCFV 数据表(HTML) 34 Page - Wolfson Microelectronics plc |
|
34 / 65 page ![]() WM8802 Product Preview w PP Rev 1.1 April 2004 34 LEFT CHANNEL RIGHT CHANNEL TLRCK (I) TBCK (I) TDATA (I) 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB 16 to 24 bits 16 to 24 bits Figure 26 Data Input Timing – Left Justified Data Input VALIDITY FLAG INPUT (VI) Validity flags can be input from RX5/VI by switching the RX5/VI input contents with VISEL. The validity flag write timing is shown below. The validity flag can be written with the micro-controller interface but port settings have priority. Writing validity flags with the micro-controller interface is done using VMODE. RX5/VI OUTPUT CONDITIONS 0 No error 1 Error Table 15 RX5/V1 Input V-L2 V-R2 V-L3 V-R1 V-L1 L1 L2 L3 R2 R1 TLRCK TBCK VI Internal latch signal Figure 27 Validity Flag Input Timing |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |