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WM8802SCFV 数据表(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8802SCFV 数据表(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 65 page  WM8802 Product Preview w PP Rev 1.1 April 2004 30 RDATA Output starts from the RLRCK edge immediately after RERR flag is lowered RERR Internal clock signal RLRCK Data 45 ms to 300 ms OK Figure 21 Internal Lock Signal CHANNEL STATUS OUTPUT DATA CATEGORY SPECIFICATION BIT 1 OUTPUT ( AUDIO ) The AUDIO pin outputs bit 1 of the channel status indicating that the input bi-phase data is PCM audio data. AUDIO status is immediately output upon detection of RERR even during High output. An output ORed with IEC61937 or the DTS-CD/LD detection flag is also possible with AOSEL. AUDIO OUTPUT CONDITIONS 0 PCM audio data (CS bit 1 = Low) 1 Non-audio data (CS bit 1 = High Table 12 AUDIO Output EMPHASIS INFORMATION OUTPUT (EMPHA) The EMPHA pin output indicates that the signal has the presence or absence of 50/15 µs emphasis for consumer and broadcast studio. EMPHA status is immediately output upon detection of RERR even during High output. EMPHA OUTPUT CONDITIONS 0 No pre-emphasis 1 50/15 µs pre-emphasis Table 13 EMPHA Output |
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