WM8802SCFV datasheet(48/65 Pages) WOLFSON

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WM8802

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PP Rev 1.1 April 2004

Output data format setting:

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

CAU

CAL

DI15

DI14

DI13

DI12

DI11

DI10

DI9

DI8

CCB address; 0xE8;

Command address: 7

SLRCKP

SBCKP

RLRCKP

RBCKP

OFSEL2

OFSEL1

OFSEL0

OFSEL [2:0]

Audio data output format setting

000: I

2S data output (initial value)

001: Left Justified data output

010: 24 bit Right Justified data output (master mode only)

011: 20 bit Right Justified data output (master mode only)

100: 16 bit Right Justified data output (master mode only)

101: Reserved

110: Reserved

111: Reserved

RBCKP

RBCK output polarity setting

0: Falling RDATA data change (initial value)

1: Rising RDATA data change

RLRCKP

RLRCK output polarity setting

0: Low period: L-channel data; High period: R-channel data (initial value)

1: Low period: R-channel data; High period: L-channel data

SBCKP

SBCK output polarity setting

0: Falling RDATA data change (initial value)

1: Falling RDATA data change

SLRCKP

SLRCK output polarity setting

0: Low period: L-channel data; High period: R-channel data (initial value)

1: Low period: R-channel data; High period: L-channel data

The data output format and RLRCK output polarity can be set independently. The RLRCH polarity is

set according to each data output format.

WM8802SCFV 数据表(PDF) 48 Page - Wolfson Microelectronics plc

WM8802SCFV 数据表(HTML) 48 Page - Wolfson Microelectronics plc

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