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WM8802SCFV 数据表(PDF) 38 Page - Wolfson Microelectronics plc

部件名 WM8802SCFV
功能描述  Digital Audio Interface Transceiver
PDF  65 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8802SCFV 数据表(HTML) 38 Page - Wolfson Microelectronics plc

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WM8802
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PP Rev 1.1 April 2004
38
REGISTER INPUT/OUTPUT
CONTENTS
R/W
CCB
ADDRESS
B0
B1
B2
B3
A0
A1
A2
A3
Function setting data input
write
0xE8
0
0
0
1
0
1
1
1
CS data input
write
0xE9
1
0
0
1
0
1
1
1
Interrupt data output
read
0xEA
0
1
0
1
0
1
1
1
fs data output
read
0xEB
1
1
0
1
0
1
1
1
CS data output
read
0xEC
0
0
1
1
0
1
1
1
Pc data output
read
0xED
1
0
1
1
0
1
1
1
Table 17 Relationship between Register Input/Output Contents and CCB Addresses
DATA WRITE METHOD
Input is performed in the following sequence: CCB addresses of A0 to A3 and B0 to B3, chip
addresses of DI0 and DI1, command addresses of DI4 to DI7 and data of DI8 to DI15. DI2 and DI3
are reserved for the system and should always be set to "0".
For the chip addresses, DI0 corresponds to CAL (low-order) and DI1 corresponds to CAU (high-
order).
DATA READ METHOD
Read data is output from DO. DO is in the high impedance state when CE is Low and begins
outputting at the rising edge of CE after the register address is recognised. DO then returns to the
high impedance state at the falling edge of CE.
If DO outputs using multiple WM8802 units are to be shared the DO outputs of the WM8802 can be
set to in a high impedance state using DOEN, This will prevent any misreading of registers from an
unselected device.
INPUT/OUTPUT TIMINGS
B0
DI0
….
A3
A2
A1
A0
B3
B2
B1
DI15
DI5
DI4
DI3
DI2
DI1
DI
DO
Hi-Z
CL
CE
Figure 30 Input Timing Chart (Normal, Low Clock)



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